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ScheduleDAGInstrs: Slightly simplify code; NFC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286510 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2016-11-10 22:11:00 +00:00
parent 7a98835990
commit fc1b3b34fd
1 changed files with 12 additions and 20 deletions
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32
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -255,13 +255,12 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
for (const MachineOperand &MO : ExitMI->operands()) { for (const MachineOperand &MO : ExitMI->operands()) {
if (!MO.isReg() || MO.isDef()) continue; if (!MO.isReg() || MO.isDef()) continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Reg == 0) continue; if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
if (TRI->isPhysicalRegister(Reg))
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
else if (MO.readsReg()) // ignore undef operands } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO)); addVRegUseDeps(&ExitSU, ExitMI->getOperandNo(&MO));
} }
}
} else { } else {
// For others, e.g. fallthrough, conditional branch, assume the exit // For others, e.g. fallthrough, conditional branch, assume the exit
// uses all the registers that are livein to the successor blocks. // uses all the registers that are livein to the successor blocks.
@ -323,6 +322,7 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
MachineInstr *MI = SU->getInstr(); MachineInstr *MI = SU->getInstr();
MachineOperand &MO = MI->getOperand(OperIdx); MachineOperand &MO = MI->getOperand(OperIdx);
unsigned Reg = MO.getReg();
// Optionally add output and anti dependencies. For anti // Optionally add output and anti dependencies. For anti
// dependencies we use a latency of 0 because for a multi-issue // dependencies we use a latency of 0 because for a multi-issue
@ -331,8 +331,7 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
// TODO: Using a latency of 1 here for output dependencies assumes // TODO: Using a latency of 1 here for output dependencies assumes
// there's no cost for reusing registers. // there's no cost for reusing registers.
SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) {
Alias.isValid(); ++Alias) {
if (!Defs.contains(*Alias)) if (!Defs.contains(*Alias))
continue; continue;
for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) { for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
@ -359,13 +358,11 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
// Either insert a new Reg2SUnits entry with an empty SUnits list, or // Either insert a new Reg2SUnits entry with an empty SUnits list, or
// retrieve the existing SUnits list for this register's uses. // retrieve the existing SUnits list for this register's uses.
// Push this SUnit on the use list. // Push this SUnit on the use list.
Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg())); Uses.insert(PhysRegSUOper(SU, OperIdx, Reg));
if (RemoveKillFlags) if (RemoveKillFlags)
MO.setIsKill(false); MO.setIsKill(false);
} } else {
else {
addPhysRegDataDeps(SU, OperIdx); addPhysRegDataDeps(SU, OperIdx);
unsigned Reg = MO.getReg();
// clear this register's use list // clear this register's use list
if (Uses.contains(Reg)) if (Uses.contains(Reg))
@ -954,12 +951,9 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
if (!MO.isReg() || !MO.isDef()) if (!MO.isReg() || !MO.isDef())
continue; continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Reg == 0) if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
continue;
if (TRI->isPhysicalRegister(Reg))
addPhysRegDeps(SU, j); addPhysRegDeps(SU, j);
else { } else if (TargetRegisterInfo::isVirtualRegister(Reg)) {
HasVRegDef = true; HasVRegDef = true;
addVRegDefDeps(SU, j); addVRegDefDeps(SU, j);
} }
@ -974,14 +968,12 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
if (!MO.isReg() || !MO.isUse()) if (!MO.isReg() || !MO.isUse())
continue; continue;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Reg == 0) if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
continue;
if (TRI->isPhysicalRegister(Reg))
addPhysRegDeps(SU, j); addPhysRegDeps(SU, j);
else if (MO.readsReg()) // ignore undef operands } else if (TargetRegisterInfo::isVirtualRegister(Reg) && MO.readsReg()) {
addVRegUseDeps(SU, j); addVRegUseDeps(SU, j);
} }
}
// If we haven't seen any uses in this scheduling region, create a // If we haven't seen any uses in this scheduling region, create a
// dependence edge to ExitSU to model the live-out latency. This is required // dependence edge to ExitSU to model the live-out latency. This is required