mirror of
https://github.com/RPCSX/llvm.git
synced 2024-12-09 20:54:06 +00:00
Do not reassociate expressions with i1 type. SimplifyCFG converts some
short-circuited conditions to AND/OR expressions, and those expressions are often converted back to a short-circuited form in code gen. The original source order may have been optimized to take advantage of the expected values, and if we reassociate them, we change the order and subvert that optimization. Radar 7497329. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95333 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
85bb54f964
commit
fc375d2200
@ -933,6 +933,15 @@ void Reassociate::ReassociateBB(BasicBlock *BB) {
|
||||
isa<VectorType>(BI->getType()))
|
||||
continue; // Floating point ops are not associative.
|
||||
|
||||
// Do not reassociate boolean (i1) expressions. We want to preserve the
|
||||
// original order of evaluation for short-circuited comparisons that
|
||||
// SimplifyCFG has folded to AND/OR expressions. If the expression
|
||||
// is not further optimized, it is likely to be transformed back to a
|
||||
// short-circuited form for code gen, and the source order may have been
|
||||
// optimized for the most likely conditions.
|
||||
if (BI->getType()->isInteger(1))
|
||||
continue;
|
||||
|
||||
// If this is a subtract instruction which is not already in negate form,
|
||||
// see if we can convert it to X+-Y.
|
||||
if (BI->getOpcode() == Instruction::Sub) {
|
||||
|
Loading…
Reference in New Issue
Block a user