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[AMDGPU][MC] Corrected src0 size for s_cbranch_join

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Fix for bug 28159: https://bugs.llvm.org//show_bug.cgi?id=28159

Reviewers: vpykhtin, arsenm

Differential Revision: https://reviews.llvm.org/D31595

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300055 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dmitry Preobrazhensky 2017-04-12 12:40:19 +00:00
parent 2778098e17
commit fcce15e390
3 changed files with 19 additions and 5 deletions
lib/Target/AMDGPU
SOPInstructions.td
test/MC
AMDGPU
sop1.s
Disassembler/AMDGPU
sop1_vi.txt

8
lib/Target/AMDGPU/SOPInstructions.td

@ -82,6 +82,12 @@ class SOP1_0_32 <string opName, list<dag> pattern = []> : SOP1_Pseudo <
let has_sdst = 0;
}
class SOP1_0_32R <string opName, list<dag> pattern = []> : SOP1_Pseudo <
opName, (outs), (ins SReg_32:$src0),
"$src0", pattern> {
let has_sdst = 0;
}
class SOP1_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),
"$sdst, $src0", pattern
@ -210,7 +216,7 @@ def S_MOVRELD_B32 : SOP1_32 <"s_movreld_b32">;
def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">;
} // End Uses = [M0]
def S_CBRANCH_JOIN : SOP1_1 <"s_cbranch_join">;
def S_CBRANCH_JOIN : SOP1_0_32R <"s_cbranch_join">;
def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">;
let Defs = [SCC] in {
def S_ABS_I32 : SOP1_32 <"s_abs_i32">;

14
test/MC/AMDGPU/sop1.s

@ -232,9 +232,17 @@ s_movreld_b64 s[2:3], s[4:5]
// SICI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x31,0x82,0xbe]
// VI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe]
s_cbranch_join s[4:5]
// SICI: s_cbranch_join s[4:5] ; encoding: [0x04,0x32,0x80,0xbe]
// VI: s_cbranch_join s[4:5] ; encoding: [0x04,0x2e,0x80,0xbe]
s_cbranch_join s4
// SICI: s_cbranch_join s4 ; encoding: [0x04,0x32,0x80,0xbe]
// VI: s_cbranch_join s4 ; encoding: [0x04,0x2e,0x80,0xbe]
s_cbranch_join 1
// NOSICI: error: invalid operand for instruction
// NOVI: error: invalid operand for instruction
s_cbranch_join 100
// NOSICI: error: invalid operand for instruction
// NOVI: error: invalid operand for instruction
s_abs_i32 s1, s2
// SICI: s_abs_i32 s1, s2 ; encoding: [0x02,0x34,0x81,0xbe]

2
test/MC/Disassembler/AMDGPU/sop1_vi.txt

@ -165,7 +165,7 @@
# VI: s_movreld_b64 s[2:3], s[4:5] ; encoding: [0x04,0x2d,0x82,0xbe]
0x04 0x2d 0x82 0xbe
# VI: s_cbranch_join s[4:5] ; encoding: [0x04,0x2e,0x80,0xbe]
# VI: s_cbranch_join s4 ; encoding: [0x04,0x2e,0x80,0xbe]
0x04 0x2e 0x80 0xbe
# VI: s_abs_i32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe]