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Fix PR18054
- Fix bug in (vsext (vzext x)) -> (vsext x) in SIGN_EXTEND_IN_REG lowering where we need to check whether x is a vector type (in-reg type) of i8, i16 or i32; otherwise, that optimization is not valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195779 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -13166,19 +13166,27 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
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// fall through
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case MVT::v4i32:
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case MVT::v8i16: {
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// (sext (vzext x)) -> (vsext x)
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SDValue Op0 = Op.getOperand(0);
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SDValue Op00 = Op0.getOperand(0);
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SDValue Tmp1;
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// Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
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if (Op0.getOpcode() == ISD::BITCAST &&
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Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
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Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
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// (sext (vzext x)) -> (vsext x)
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Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
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if (Tmp1.getNode()) {
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SDValue Tmp1Op0 = Tmp1.getOperand(0);
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assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
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"This optimization is invalid without a VZEXT.");
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return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
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if (Tmp1.getNode()) {
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EVT ExtraEltVT = ExtraVT.getVectorElementType();
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// This folding is only valid when the in-reg type is a vector of i8,
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// i16, or i32.
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if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
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ExtraEltVT == MVT::i32) {
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SDValue Tmp1Op0 = Tmp1.getOperand(0);
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assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
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"This optimization is invalid without a VZEXT.");
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return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
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}
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Op0 = Tmp1;
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}
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}
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// If the above didn't work, then just use Shift-Left + Shift-Right.
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10
test/CodeGen/X86/pr18054.ll
Normal file
10
test/CodeGen/X86/pr18054.ll
Normal file
@ -0,0 +1,10 @@
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=penryn | FileCheck %s
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define void @foo(<16 x i32>* %p, <16 x i1> %x) {
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%ret = sext <16 x i1> %x to <16 x i32>
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store <16 x i32> %ret, <16 x i32>* %p
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ret void
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; CHECK: foo
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; CHECK-NOT: pmovsxbd
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; CHECK: ret
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}
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