From fd444b2a694dd4421d9ac3672f432aa501de17ce Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 19 Aug 2005 00:16:17 +0000 Subject: [PATCH] Stop adding bogus operands to variable shifts on X86. These instructions only take one operand. The other comes implicitly in through CL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22887 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelPattern.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index 7bf481faf8f..e78a9df62c8 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -3223,7 +3223,7 @@ unsigned ISel::SelectExpr(SDOperand N) { case MVT::i32: Opc = X86::SHL32rCL; break; } BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2); - BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2); + BuildMI(BB, Opc, 1, Result).addReg(Tmp1); return Result; case ISD::SRL: if (ConstantSDNode *CN = dyn_cast(N.getOperand(1))) { @@ -3253,7 +3253,7 @@ unsigned ISel::SelectExpr(SDOperand N) { case MVT::i32: Opc = X86::SHR32rCL; break; } BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(Tmp2); - BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2); + BuildMI(BB, Opc, 1, Result).addReg(Tmp1); return Result; case ISD::SRA: if (ConstantSDNode *CN = dyn_cast(N.getOperand(1))) {