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ARM: Do not attempt to modify register class of physregs.

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Physregs have no associated register class, do not attempt to modify it
in Thumb2InstrInfo::storeRegToStackSlot()/loadFromStackSlot().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271339 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2016-05-31 21:39:12 +00:00
parent 6d33ed3ca2
commit fe23302cc8
2 changed files with 20 additions and 4 deletions
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13
lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -148,8 +148,10 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
// Thumb2 STRD expects its dest-registers to be in rGPR. Not a problem for
// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
// otherwise).
MachineRegisterInfo *MRI = &MF.getRegInfo();
MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
MachineRegisterInfo *MRI = &MF.getRegInfo();
MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
}
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
@ -187,8 +189,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
// Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
// gsub_0, but needs an extra constraint for gsub_1 (which could be sp
// otherwise).
MachineRegisterInfo *MRI = &MF.getRegInfo();
MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
MachineRegisterInfo *MRI = &MF.getRegInfo();
MRI->constrainRegClass(DestReg,
&ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
}
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);

11
test/CodeGen/ARM/cmpxchg-O0.ll
View File

@ -100,3 +100,14 @@ define { i64, i1 } @test_nontrivial_args(i64* %addr, i64 %desired, i64 %new) {
%res = cmpxchg i64* %addr, i64 %desired1, i64 %new1 seq_cst seq_cst
ret { i64, i1 } %res
}
; The following used to trigger an assertion in the aarch64 backend when
; creating a spill for a physreg with RC==GPRPairRegClass.
; CHECK-LABEL: test_cmpxchg_spillbug:
; CHECK: ldrexd
; CHECK: strexd
; CHECK: bne
define void @test_cmpxchg_spillbug() {
%v = cmpxchg i64* undef, i64 undef, i64 undef seq_cst seq_cst
ret void
}