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Reduce use of pseudo ops

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Namely, output the rellocation flags explicitly when loading constants.
Added benifit: save a load when loading from the constant pool.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22296 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-06-27 17:15:36 +00:00
parent b72bcbb42b
commit fe895e3d87
2 changed files with 41 additions and 8 deletions
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33
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -852,6 +852,18 @@ static unsigned GetSymVersion(unsigned opcode)
case Alpha::STB: return Alpha::STB_SYM;
}
}
static unsigned GetRelVersion(unsigned opcode)
{
switch (opcode) {
default: assert(0 && "unknown load or store"); return 0;
case Alpha::LDQ: return Alpha::LDQr;
case Alpha::LDS: return Alpha::LDSr;
case Alpha::LDT: return Alpha::LDTr;
case Alpha::LDL: return Alpha::LDLr;
case Alpha::LDBU: return Alpha::LDBUr;
case Alpha::LDWU: return Alpha::LDWUr;
}
}
void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
{
@ -1234,9 +1246,11 @@ unsigned AlphaISel::SelectExprFP(SDOperand N, unsigned Result)
}
else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
AlphaLowering.restoreGP(BB);
Opc = GetSymVersion(Opc);
Opc = GetRelVersion(Opc);
has_sym = true;
BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
Tmp1 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex()).addReg(Alpha::R29);
BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
}
else if(Address.getOpcode() == ISD::FrameIndex) {
BuildMI(BB, Opc, 2, Result)
@ -1321,7 +1335,9 @@ unsigned AlphaISel::SelectExprFP(SDOperand N, unsigned Result)
{
AlphaLowering.restoreGP(BB);
has_sym = true;
BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1).addConstantPoolIndex(CP->getIndex());
Tmp2 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(CP->getIndex()).addReg(Alpha::R29);
BuildMI(BB, Alpha::LDSr, 2, Tmp1).addConstantPoolIndex(CP->getIndex()).addReg(Tmp2);
}
else if(Address.getOpcode() == ISD::FrameIndex) {
Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
@ -1532,9 +1548,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
}
else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
AlphaLowering.restoreGP(BB);
Opc = GetSymVersion(Opc);
Opc = GetRelVersion(Opc);
has_sym = true;
BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
Tmp1 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex()).addReg(Alpha::R29);
BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
}
else if(Address.getOpcode() == ISD::FrameIndex) {
BuildMI(BB, Opc, 2, Result)
@ -2219,7 +2237,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
ConstantUInt *C = ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
unsigned CPI = CP->getConstantPoolIndex(C);
AlphaLowering.restoreGP(BB);
BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(CPI);
has_sym = true;
Tmp1 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI).addReg(Alpha::R29);
BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
}
return Result;
}

16
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -333,7 +333,6 @@ let isCall = 1,
def JSR_COROUTINE : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jsr_coroutine $RD,($RS),1">; //Jump to subroutine return
def BR : BForm<0x30, (ops GPRC:$RD, s21imm:$DISP), "br $RD,$DISP">; //Branch
let Uses = [R28] in {
//Stores, int
def STB : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB)">; // Store byte
def STW : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB)">; // Store word
@ -353,13 +352,26 @@ def STT : MForm<0x27, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "stt $RA,$DISP($RB
//Loads, float
def LDS : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB)">; //Load S_floating
def LDT : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB)">; //Load T_floating
}
//Load address
def LDA : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB)">; //Load address
def LDAH : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB)">; //Load address high
//Loads, int, Rellocated form
def LDLr : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($RB) !gprellow">; // Load sign-extended longword
def LDQr : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
def LDBUr : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
def LDWUr : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
//Loads, float, Rellocated form
def LDSr : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB) !gprellow">; //Load S_floating
def LDTr : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
//Load address, rellocated form
def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB) !gprelhigh">; //Load address high
//Branches, int
def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero
def BGE : BForm<0x3E, (ops GPRC:$RA, s21imm:$DISP), "bge $RA,$DISP">; //Branch if >= zero