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[MCTargetAsmParser] Move the member varialbes that reference

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MCSubtargetInfo in the subclasses into MCTargetAsmParser and define a
member function getSTI.

This is done in preparation for making changes to shrink the size of
MCRelaxableFragment. (see http://reviews.llvm.org/D14346).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253124 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2015-11-14 05:20:05 +00:00
parent d1b0795570
commit ff528b6f03
12 changed files with 143 additions and 115 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
include/llvm/MC/MCTargetAsmParser.h
View File

@ -20,6 +20,7 @@ class AsmToken;
class MCInst;
class MCParsedAsmOperand;
class MCStreamer;
class MCSubtargetInfo;
class SMLoc;
class StringRef;
template <typename T> class SmallVectorImpl;
@ -92,7 +93,7 @@ private:
MCTargetAsmParser(const MCTargetAsmParser &) = delete;
void operator=(const MCTargetAsmParser &) = delete;
protected: // Can only create subclasses.
MCTargetAsmParser(MCTargetOptions const &);
MCTargetAsmParser(MCTargetOptions const &, MCSubtargetInfo &STI);
/// AvailableFeatures - The current set of available features.
uint64_t AvailableFeatures;
@ -107,9 +108,14 @@ protected: // Can only create subclasses.
/// Set of options which affects instrumentation of inline assembly.
MCTargetOptions MCOptions;
/// Current STI.
MCSubtargetInfo &STI;
public:
~MCTargetAsmParser() override;
const MCSubtargetInfo &getSTI() const;
uint64_t getAvailableFeatures() const { return AvailableFeatures; }
void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; }

11
lib/MC/MCParser/MCTargetAsmParser.cpp
View File

@ -7,13 +7,20 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCTargetAsmParser.h"
using namespace llvm;
MCTargetAsmParser::MCTargetAsmParser(MCTargetOptions const &MCOptions)
: AvailableFeatures(0), ParsingInlineAsm(false), MCOptions(MCOptions)
MCTargetAsmParser::MCTargetAsmParser(MCTargetOptions const &MCOptions,
MCSubtargetInfo &STI)
: AvailableFeatures(0), ParsingInlineAsm(false), MCOptions(MCOptions),
STI(STI)
{
}
MCTargetAsmParser::~MCTargetAsmParser() {
}
const MCSubtargetInfo &MCTargetAsmParser::getSTI() const {
return STI;
}

28
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -43,7 +43,6 @@ class AArch64Operand;
class AArch64AsmParser : public MCTargetAsmParser {
private:
StringRef Mnemonic; ///< Instruction mnemonic.
MCSubtargetInfo &STI;
// Map of register aliases registers via the .req directive.
StringMap<std::pair<bool, unsigned> > RegisterReqs;
@ -117,14 +116,14 @@ public:
};
AArch64AsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options), STI(STI) {
: MCTargetAsmParser(Options, STI) {
MCAsmParserExtension::Initialize(Parser);
MCStreamer &S = getParser().getStreamer();
if (S.getTargetStreamer() == nullptr)
new AArch64TargetStreamer(S);
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
}
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
@ -2043,7 +2042,7 @@ AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
bool Valid;
auto Mapper = AArch64PRFM::PRFMMapper();
StringRef Name =
Mapper.toString(MCE->getValue(), STI.getFeatureBits(), Valid);
Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid);
Operands.push_back(AArch64Operand::CreatePrefetch(prfop, Name,
S, getContext()));
return MatchOperand_Success;
@ -2057,7 +2056,7 @@ AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
bool Valid;
auto Mapper = AArch64PRFM::PRFMMapper();
unsigned prfop =
Mapper.fromString(Tok.getString(), STI.getFeatureBits(), Valid);
Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid);
if (!Valid) {
TokError("pre-fetch hint expected");
return MatchOperand_ParseFail;
@ -2671,7 +2670,7 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
bool Valid;
auto Mapper = AArch64DB::DBarrierMapper();
StringRef Name =
Mapper.toString(MCE->getValue(), STI.getFeatureBits(), Valid);
Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid);
Operands.push_back( AArch64Operand::CreateBarrier(MCE->getValue(), Name,
ExprLoc, getContext()));
return MatchOperand_Success;
@ -2685,7 +2684,7 @@ AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
bool Valid;
auto Mapper = AArch64DB::DBarrierMapper();
unsigned Opt =
Mapper.fromString(Tok.getString(), STI.getFeatureBits(), Valid);
Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid);
if (!Valid) {
TokError("invalid barrier option name");
return MatchOperand_ParseFail;
@ -2714,20 +2713,21 @@ AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
bool IsKnown;
auto MRSMapper = AArch64SysReg::MRSMapper();
uint32_t MRSReg = MRSMapper.fromString(Tok.getString(), STI.getFeatureBits(),
IsKnown);
uint32_t MRSReg = MRSMapper.fromString(Tok.getString(),
getSTI().getFeatureBits(), IsKnown);
assert(IsKnown == (MRSReg != -1U) &&
"register should be -1 if and only if it's unknown");
auto MSRMapper = AArch64SysReg::MSRMapper();
uint32_t MSRReg = MSRMapper.fromString(Tok.getString(), STI.getFeatureBits(),
IsKnown);
uint32_t MSRReg = MSRMapper.fromString(Tok.getString(),
getSTI().getFeatureBits(), IsKnown);
assert(IsKnown == (MSRReg != -1U) &&
"register should be -1 if and only if it's unknown");
auto PStateMapper = AArch64PState::PStateMapper();
uint32_t PStateField =
PStateMapper.fromString(Tok.getString(), STI.getFeatureBits(), IsKnown);
PStateMapper.fromString(Tok.getString(),
getSTI().getFeatureBits(), IsKnown);
assert(IsKnown == (PStateField != -1U) &&
"register should be -1 if and only if it's unknown");
@ -3990,7 +3990,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return true;
Inst.setLoc(IDLoc);
Out.EmitInstruction(Inst, STI);
Out.EmitInstruction(Inst, getSTI());
return false;
}
case Match_MissingFeature: {
@ -4203,7 +4203,7 @@ bool AArch64AsmParser::parseDirectiveTLSDescCall(SMLoc L) {
Inst.setOpcode(AArch64::TLSDESCCALL);
Inst.addOperand(MCOperand::createExpr(Expr));
getParser().getStreamer().EmitInstruction(Inst, STI);
getParser().getStreamer().EmitInstruction(Inst, getSTI());
return false;
}

16
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -327,14 +327,13 @@ public:
};
class AMDGPUAsmParser : public MCTargetAsmParser {
MCSubtargetInfo &STI;
const MCInstrInfo &MII;
MCAsmParser &Parser;
unsigned ForcedEncodingSize;
bool isVI() const {
return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
return getSTI().getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
}
bool hasSGPR102_SGPR103() const {
@ -368,15 +367,14 @@ public:
AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options)
: MCTargetAsmParser(Options), STI(STI), MII(MII), Parser(_Parser),
: MCTargetAsmParser(Options, STI), MII(MII), Parser(_Parser),
ForcedEncodingSize(0) {
if (STI.getFeatureBits().none()) {
if (getSTI().getFeatureBits().none()) {
// Set default features.
STI.ToggleFeature("SOUTHERN_ISLANDS");
}
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
}
AMDGPUTargetStreamer &getTargetStreamer() {
@ -603,7 +601,7 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
default: break;
case Match_Success:
Inst.setLoc(IDLoc);
Out.EmitInstruction(Inst, STI);
Out.EmitInstruction(Inst, getSTI());
return false;
case Match_MissingFeature:
return Error(IDLoc, "instruction not supported on this GPU");
@ -697,7 +695,7 @@ bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
// If this directive has no arguments, then use the ISA version for the
// targeted GPU.
if (getLexer().is(AsmToken::EndOfStatement)) {
AMDGPU::IsaVersion Isa = AMDGPU::getIsaVersion(STI.getFeatureBits());
AMDGPU::IsaVersion Isa = AMDGPU::getIsaVersion(getSTI().getFeatureBits());
getTargetStreamer().EmitDirectiveHSACodeObjectISA(Isa.Major, Isa.Minor,
Isa.Stepping,
"AMD", "AMDGPU");
@ -909,7 +907,7 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
amd_kernel_code_t Header;
AMDGPU::initDefaultAMDKernelCodeT(Header, STI.getFeatureBits());
AMDGPU::initDefaultAMDKernelCodeT(Header, getSTI().getFeatureBits());
while (true) {

33
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -129,7 +129,6 @@ public:
};
class ARMAsmParser : public MCTargetAsmParser {
MCSubtargetInfo &STI;
const MCInstrInfo &MII;
const MCRegisterInfo *MRI;
UnwindContext UC;
@ -247,40 +246,40 @@ class ARMAsmParser : public MCTargetAsmParser {
OperandVector &Operands);
bool isThumb() const {
// FIXME: Can tablegen auto-generate this?
return STI.getFeatureBits()[ARM::ModeThumb];
return getSTI().getFeatureBits()[ARM::ModeThumb];
}
bool isThumbOne() const {
return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2];
return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
}
bool isThumbTwo() const {
return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2];
return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
}
bool hasThumb() const {
return STI.getFeatureBits()[ARM::HasV4TOps];
return getSTI().getFeatureBits()[ARM::HasV4TOps];
}
bool hasV6Ops() const {
return STI.getFeatureBits()[ARM::HasV6Ops];
return getSTI().getFeatureBits()[ARM::HasV6Ops];
}
bool hasV6MOps() const {
return STI.getFeatureBits()[ARM::HasV6MOps];
return getSTI().getFeatureBits()[ARM::HasV6MOps];
}
bool hasV7Ops() const {
return STI.getFeatureBits()[ARM::HasV7Ops];
return getSTI().getFeatureBits()[ARM::HasV7Ops];
}
bool hasV8Ops() const {
return STI.getFeatureBits()[ARM::HasV8Ops];
return getSTI().getFeatureBits()[ARM::HasV8Ops];
}
bool hasARM() const {
return !STI.getFeatureBits()[ARM::FeatureNoARM];
return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
}
bool hasDSP() const {
return STI.getFeatureBits()[ARM::FeatureDSP];
return getSTI().getFeatureBits()[ARM::FeatureDSP];
}
bool hasD16() const {
return STI.getFeatureBits()[ARM::FeatureD16];
return getSTI().getFeatureBits()[ARM::FeatureD16];
}
bool hasV8_1aOps() const {
return STI.getFeatureBits()[ARM::HasV8_1aOps];
return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
}
void SwitchMode() {
@ -288,7 +287,7 @@ class ARMAsmParser : public MCTargetAsmParser {
setAvailableFeatures(FB);
}
bool isMClass() const {
return STI.getFeatureBits()[ARM::FeatureMClass];
return getSTI().getFeatureBits()[ARM::FeatureMClass];
}
/// @name Auto-generated Match Functions
@ -351,7 +350,7 @@ public:
ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options), STI(STI), MII(MII), UC(Parser) {
: MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
MCAsmParserExtension::Initialize(Parser);
// Cache the MCRegisterInfo.
@ -8611,7 +8610,7 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return false;
Inst.setLoc(IDLoc);
Out.EmitInstruction(Inst, STI);
Out.EmitInstruction(Inst, getSTI());
return false;
case Match_MissingFeature: {
assert(ErrorInfo && "Unknown missing feature!");
@ -9166,7 +9165,7 @@ bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
// FIXME: This is using table-gen data, but should be moved to
// ARMTargetParser once that is table-gen'd.
if (!STI.isCPUStringValid(CPU)) {
if (!getSTI().isCPUStringValid(CPU)) {
Error(L, "Unknown CPU name");
return false;
}

15
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
View File

@ -76,7 +76,6 @@ class HexagonAsmParser : public MCTargetAsmParser {
return static_cast<HexagonTargetStreamer &>(TS);
}
MCSubtargetInfo &STI;
MCAsmParser &Parser;
MCAssembler *Assembler;
MCInstrInfo const &MCII;
@ -136,10 +135,9 @@ class HexagonAsmParser : public MCTargetAsmParser {
public:
HexagonAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options), STI(_STI), Parser(_Parser),
: MCTargetAsmParser(Options, _STI), Parser(_Parser),
MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
setAvailableFeatures(
ComputeAvailableFeatures(_STI.getFeatureBits()));
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
MCAsmParserExtension::Initialize(_Parser);
@ -627,10 +625,11 @@ bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
// Check the bundle for errors.
const MCRegisterInfo *RI = getContext().getRegisterInfo();
HexagonMCChecker Check(MCII, STI, MCB, MCB, *RI);
HexagonMCChecker Check(MCII, getSTI(), MCB, MCB, *RI);
bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, STI, getContext(),
MCB, &Check);
bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(),
getContext(), MCB,
&Check);
while (Check.getNextErrInfo() == true) {
unsigned Reg = Check.getErrRegister();
@ -715,7 +714,7 @@ bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
// Empty packets are valid yet aren't emitted
return false;
}
Out.EmitInstruction(MCB, STI);
Out.EmitInstruction(MCB, getSTI());
} else {
// If compounding and duplexing didn't reduce the size below
// 4 or less we have a packet that is too big.

99
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -107,7 +107,6 @@ class MipsAsmParser : public MCTargetAsmParser {
return static_cast<MipsTargetStreamer &>(TS);
}
MCSubtargetInfo &STI;
MipsABIInfo ABI;
SmallVector<std::unique_ptr<MipsAssemblerOptions>, 2> AssemblerOptions;
MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a
@ -356,7 +355,7 @@ class MipsAsmParser : public MCTargetAsmParser {
}
void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
if (!(STI.getFeatureBits()[Feature])) {
if (!(getSTI().getFeatureBits()[Feature])) {
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
@ -364,7 +363,7 @@ class MipsAsmParser : public MCTargetAsmParser {
}
void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
if (STI.getFeatureBits()[Feature]) {
if (getSTI().getFeatureBits()[Feature]) {
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
@ -373,12 +372,12 @@ class MipsAsmParser : public MCTargetAsmParser {
void setModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
setFeatureBits(Feature, FeatureString);
AssemblerOptions.front()->setFeatures(STI.getFeatureBits());
AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
}
void clearModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
clearFeatureBits(Feature, FeatureString);
AssemblerOptions.front()->setFeatures(STI.getFeatureBits());
AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
}
public:
@ -391,7 +390,7 @@ public:
MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options), STI(sti),
: MCTargetAsmParser(Options, sti),
ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
sti.getCPU(), Options)) {
MCAsmParserExtension::Initialize(parser);
@ -399,15 +398,15 @@ public:
parser.addAliasForDirective(".asciiz", ".asciz");
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
// Remember the initial assembler options. The user can not modify these.
AssemblerOptions.push_back(
llvm::make_unique<MipsAssemblerOptions>(STI.getFeatureBits()));
llvm::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
// Create an assembler options environment for the user to modify.
AssemblerOptions.push_back(
llvm::make_unique<MipsAssemblerOptions>(STI.getFeatureBits()));
llvm::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));
getTargetStreamer().updateABIInfo(*this);
@ -433,63 +432,87 @@ public:
/// True if all of $fcc0 - $fcc7 exist for the current ISA.
bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
bool isGP64bit() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
bool isFP64bit() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
bool isGP64bit() const {
return getSTI().getFeatureBits()[Mips::FeatureGP64Bit];
}
bool isFP64bit() const {
return getSTI().getFeatureBits()[Mips::FeatureFP64Bit];
}
const MipsABIInfo &getABI() const { return ABI; }
bool isABI_N32() const { return ABI.IsN32(); }
bool isABI_N64() const { return ABI.IsN64(); }
bool isABI_O32() const { return ABI.IsO32(); }
bool isABI_FPXX() const { return STI.getFeatureBits()[Mips::FeatureFPXX]; }
bool isABI_FPXX() const {
return getSTI().getFeatureBits()[Mips::FeatureFPXX];
}
bool useOddSPReg() const {
return !(STI.getFeatureBits()[Mips::FeatureNoOddSPReg]);
return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]);
}
bool inMicroMipsMode() const {
return STI.getFeatureBits()[Mips::FeatureMicroMips];
return getSTI().getFeatureBits()[Mips::FeatureMicroMips];
}
bool hasMips1() const {
return getSTI().getFeatureBits()[Mips::FeatureMips1];
}
bool hasMips2() const {
return getSTI().getFeatureBits()[Mips::FeatureMips2];
}
bool hasMips3() const {
return getSTI().getFeatureBits()[Mips::FeatureMips3];
}
bool hasMips4() const {
return getSTI().getFeatureBits()[Mips::FeatureMips4];
}
bool hasMips5() const {
return getSTI().getFeatureBits()[Mips::FeatureMips5];
}
bool hasMips1() const { return STI.getFeatureBits()[Mips::FeatureMips1]; }
bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
bool hasMips4() const { return STI.getFeatureBits()[Mips::FeatureMips4]; }
bool hasMips5() const { return STI.getFeatureBits()[Mips::FeatureMips5]; }
bool hasMips32() const {
return STI.getFeatureBits()[Mips::FeatureMips32];
return getSTI().getFeatureBits()[Mips::FeatureMips32];
}
bool hasMips64() const {
return STI.getFeatureBits()[Mips::FeatureMips64];
return getSTI().getFeatureBits()[Mips::FeatureMips64];
}
bool hasMips32r2() const {
return STI.getFeatureBits()[Mips::FeatureMips32r2];
return getSTI().getFeatureBits()[Mips::FeatureMips32r2];
}
bool hasMips64r2() const {
return STI.getFeatureBits()[Mips::FeatureMips64r2];
return getSTI().getFeatureBits()[Mips::FeatureMips64r2];
}
bool hasMips32r3() const {
return (STI.getFeatureBits()[Mips::FeatureMips32r3]);
return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]);
}
bool hasMips64r3() const {
return (STI.getFeatureBits()[Mips::FeatureMips64r3]);
return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]);
}
bool hasMips32r5() const {
return (STI.getFeatureBits()[Mips::FeatureMips32r5]);
return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]);
}
bool hasMips64r5() const {
return (STI.getFeatureBits()[Mips::FeatureMips64r5]);
return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]);
}
bool hasMips32r6() const {
return STI.getFeatureBits()[Mips::FeatureMips32r6];
return getSTI().getFeatureBits()[Mips::FeatureMips32r6];
}
bool hasMips64r6() const {
return STI.getFeatureBits()[Mips::FeatureMips64r6];
return getSTI().getFeatureBits()[Mips::FeatureMips64r6];
}
bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
bool hasDSPR3() const { return STI.getFeatureBits()[Mips::FeatureDSPR3]; }
bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
bool hasDSP() const {
return getSTI().getFeatureBits()[Mips::FeatureDSP];
}
bool hasDSPR2() const {
return getSTI().getFeatureBits()[Mips::FeatureDSPR2];
}
bool hasDSPR3() const {
return getSTI().getFeatureBits()[Mips::FeatureDSPR3];
}
bool hasMSA() const {
return getSTI().getFeatureBits()[Mips::FeatureMSA];
}
bool hasCnMips() const {
return (STI.getFeatureBits()[Mips::FeatureCnMips]);
return (getSTI().getFeatureBits()[Mips::FeatureCnMips]);
}
bool inPicMode() {
@ -497,15 +520,15 @@ public:
}
bool inMips16Mode() const {
return STI.getFeatureBits()[Mips::FeatureMips16];
return getSTI().getFeatureBits()[Mips::FeatureMips16];
}
bool useTraps() const {
return STI.getFeatureBits()[Mips::FeatureUseTCCInDIV];
return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV];
}
bool useSoftFloat() const {
return STI.getFeatureBits()[Mips::FeatureSoftFloat];
return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
}
/// Warn if RegIndex is the same as the current AT.
@ -3289,7 +3312,7 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
if (processInstruction(Inst, IDLoc, Instructions))
return true;
for (unsigned i = 0; i < Instructions.size(); i++)
Out.EmitInstruction(Instructions[i], STI);
Out.EmitInstruction(Instructions[i], getSTI());
return false;
}
case Match_MissingFeature:

13
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
View File

@ -243,7 +243,6 @@ namespace {
struct PPCOperand;
class PPCAsmParser : public MCTargetAsmParser {
MCSubtargetInfo &STI;
const MCInstrInfo &MII;
bool IsPPC64;
bool IsDarwin;
@ -291,9 +290,9 @@ class PPCAsmParser : public MCTargetAsmParser {
public:
PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &, const MCInstrInfo &MII,
const MCTargetOptions &Options)
: MCTargetAsmParser(Options), STI(STI), MII(MII) {
PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &,
const MCInstrInfo &MII, const MCTargetOptions &Options)
: MCTargetAsmParser(Options, STI), MII(MII) {
// Check for 64-bit vs. 32-bit pointer mode.
Triple TheTriple(STI.getTargetTriple());
IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
@ -1185,7 +1184,7 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
break;
}
case PPC::MFTB: {
if (STI.getFeatureBits()[PPC::FeatureMFTB]) {
if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
assert(Inst.getNumOperands() == 2 && "Expecting two operands");
Inst.setOpcode(PPC::MFSPR);
}
@ -1205,7 +1204,7 @@ bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// Post-process instructions (typically extended mnemonics)
ProcessInstruction(Inst, Operands);
Inst.setLoc(IDLoc);
Out.EmitInstruction(Inst, STI);
Out.EmitInstruction(Inst, getSTI());
return false;
case Match_MissingFeature:
return Error(IDLoc, "instruction use requires an option to be enabled");
@ -1690,7 +1689,7 @@ bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
// where th can be omitted when it is 0. dcbtst is the same. We take the
// server form to be the default, so swap the operands if we're parsing for
// an embedded core (they'll be swapped again upon printing).
if (STI.getFeatureBits()[PPC::FeatureBookE] &&
if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
Operands.size() == 4 &&
(Name == "dcbt" || Name == "dcbtst")) {
std::swap(Operands[1], Operands[3]);

9
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
View File

@ -35,7 +35,6 @@ namespace {
class SparcOperand;
class SparcAsmParser : public MCTargetAsmParser {
MCSubtargetInfo &STI;
MCAsmParser &Parser;
/// @name Auto-generated Match Functions
@ -82,7 +81,7 @@ class SparcAsmParser : public MCTargetAsmParser {
bool parseDirectiveWord(unsigned Size, SMLoc L);
bool is64Bit() const {
return STI.getTargetTriple().getArch() == Triple::sparcv9;
return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
}
void expandSET(MCInst &Inst, SMLoc IDLoc,
@ -92,9 +91,9 @@ public:
SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options)
: MCTargetAsmParser(Options), STI(sti), Parser(parser) {
: MCTargetAsmParser(Options, sti), Parser(parser) {
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
}
};
@ -528,7 +527,7 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
}
for (const MCInst &I : Instructions) {
Out.EmitInstruction(I, STI);
Out.EmitInstruction(I, getSTI());
}
return false;
}

7
lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
View File

@ -349,7 +349,6 @@ class SystemZAsmParser : public MCTargetAsmParser {
#include "SystemZGenAsmMatcher.inc"
private:
MCSubtargetInfo &STI;
MCAsmParser &Parser;
enum RegisterGroup {
RegGR,
@ -389,11 +388,11 @@ public:
SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
const MCInstrInfo &MII,
const MCTargetOptions &Options)
: MCTargetAsmParser(Options), STI(sti), Parser(parser) {
: MCTargetAsmParser(Options, sti), Parser(parser) {
MCAsmParserExtension::Initialize(Parser);
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
}
// Override MCTargetAsmParser.
@ -793,7 +792,7 @@ bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
switch (MatchResult) {
case Match_Success:
Inst.setLoc(IDLoc);
Out.EmitInstruction(Inst, STI);
Out.EmitInstruction(Inst, getSTI());
return false;
case Match_MissingFeature: {

17
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -57,7 +57,6 @@ static const char OpPrecedence[] = {
};
class X86AsmParser : public MCTargetAsmParser {
MCSubtargetInfo &STI;
const MCInstrInfo &MII;
ParseInstructionInfo *InstInfo;
std::unique_ptr<X86AsmInstrumentation> Instrumentation;
@ -760,15 +759,15 @@ private:
bool is64BitMode() const {
// FIXME: Can tablegen auto-generate this?
return STI.getFeatureBits()[X86::Mode64Bit];
return getSTI().getFeatureBits()[X86::Mode64Bit];
}
bool is32BitMode() const {
// FIXME: Can tablegen auto-generate this?
return STI.getFeatureBits()[X86::Mode32Bit];
return getSTI().getFeatureBits()[X86::Mode32Bit];
}
bool is16BitMode() const {
// FIXME: Can tablegen auto-generate this?
return STI.getFeatureBits()[X86::Mode16Bit];
return getSTI().getFeatureBits()[X86::Mode16Bit];
}
void SwitchMode(unsigned mode) {
FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
@ -802,10 +801,10 @@ private:
public:
X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &Parser,
const MCInstrInfo &mii, const MCTargetOptions &Options)
: MCTargetAsmParser(Options), STI(sti), MII(mii), InstInfo(nullptr) {
: MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr) {
// Initialize the set of available features.
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
Instrumentation.reset(
CreateX86AsmInstrumentation(Options, Parser.getContext(), STI));
}
@ -1745,7 +1744,7 @@ std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
}
// rounding mode token
if (STI.getFeatureBits()[X86::FeatureAVX512] &&
if (getSTI().getFeatureBits()[X86::FeatureAVX512] &&
getLexer().is(AsmToken::LCurly))
return ParseRoundingModeOp(Start, End);
@ -1803,7 +1802,7 @@ std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() {
}
case AsmToken::LCurly:{
SMLoc Start = Parser.getTok().getLoc(), End;
if (STI.getFeatureBits()[X86::FeatureAVX512])
if (getSTI().getFeatureBits()[X86::FeatureAVX512])
return ParseRoundingModeOp(Start, End);
return ErrorOperand(Start, "unknown token in expression");
}
@ -1813,7 +1812,7 @@ std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() {
bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
const MCParsedAsmOperand &Op) {
MCAsmParser &Parser = getParser();
if(STI.getFeatureBits()[X86::FeatureAVX512]) {
if(getSTI().getFeatureBits()[X86::FeatureAVX512]) {
if (getLexer().is(AsmToken::LCurly)) {
// Eat "{" and mark the current place.
const SMLoc consumedToken = consumeToken();

2
utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -3052,7 +3052,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
if (HasDeprecation) {
OS << " std::string Info;\n";
OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
OS << " SMLoc Loc = ((" << Target.getName()
<< "Operand&)*Operands[0]).getStartLoc();\n";
OS << " getParser().Warning(Loc, Info, None);\n";