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https://github.com/RPCSX/llvm.git
synced 2024-12-04 10:04:33 +00:00
Fix bugs in FITOS/D instruction generation.
The space for optional args in the stack frame is now being computed, so finish the code generation for the variable `alloca'. Finally, made a major overhaul of how stack frame is managed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1194 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
parent
b9c3863e08
commit
ff5a09ee44
@ -139,11 +139,11 @@ ChooseBFpccInstruction(const InstructionNode* instrNode,
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// For now, hack this using a little static cache of TmpInstructions.
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// Eventually the entire BURG instruction selection should be put
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// into a separate class that can hold such information.
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// The static cache is not too bad because that memory for these
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// TmpInstructions will be freed elsewhere in any case.
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// The static cache is not too bad because the memory for these
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// TmpInstructions will be freed along with the rest of the Method anyway.
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//
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static TmpInstruction*
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GetTmpForCC(Value* boolVal, const Method* method)
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GetTmpForCC(Value* boolVal, const Method* method, const Type* ccType)
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{
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typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache;
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static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
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@ -157,11 +157,11 @@ GetTmpForCC(Value* boolVal, const Method* method)
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boolToTmpCache.clear();
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}
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// Look for tmpI and create a new one otherswise.
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// new value is directly written to map using
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// Look for tmpI and create a new one otherwise. The new value is
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// directly written to map using the ref returned by operator[].
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TmpInstruction*& tmpI = boolToTmpCache[boolVal];
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if (tmpI == NULL)
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tmpI = new TmpInstruction(TMP_INSTRUCTION_OPCODE, boolVal, NULL);
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tmpI = new TmpInstruction(TMP_INSTRUCTION_OPCODE, ccType, boolVal, NULL);
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return tmpI;
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}
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@ -259,9 +259,12 @@ ChooseConvertToFloatInstr(const InstructionNode* instrNode,
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break;
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case ToDoubleTy:
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if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
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opCode = FITOD;
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else if (opType == Type::LongTy)
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// Use FXTOD for all integer-to-double conversions. This has to be
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// consistent with the code in CreateCodeToCopyIntToFloat() since
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// that will be used to load the integer into an FP register.
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//
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if (opType == Type::SByteTy || opType == Type::ShortTy ||
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opType == Type::IntTy || opType == Type::LongTy)
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opCode = FXTOD;
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else if (opType == Type::FloatTy)
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opCode = FSTOD;
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@ -1033,13 +1036,22 @@ GetInstructionsForProlog(BasicBlock* entryBB,
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{
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int64_t s0=0; // used to avoid overloading ambiguity below
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const MachineFrameInfo& frameInfo = target.getFrameInfo();
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// The second operand is the stack size. If it does not fit in the
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// immediate field, we either have to find an unused register in the
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// caller's window or move some elements to the dynamically allocated
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// area of the stack frame (just above save area and method args).
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Method* method = entryBB->getParent();
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MachineCodeForMethod& mcodeInfo = method->getMachineCode();
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unsigned int staticStackSize = mcodeInfo.getStaticStackSize();
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MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
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unsigned int staticStackSize = mcInfo.getStaticStackSize();
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if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize())
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staticStackSize = (unsigned) frameInfo.getMinStackFrameSize();
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if (unsigned padsz = (staticStackSize %
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(unsigned) frameInfo.getStackFrameSizeAlignment()))
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staticStackSize += padsz;
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assert(target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)
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&& "Stack size too large for immediate field of SAVE instruction. Need additional work as described in the comment above");
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@ -1047,7 +1059,7 @@ GetInstructionsForProlog(BasicBlock* entryBB,
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mvec[0] = new MachineInstr(SAVE);
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mvec[0]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
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mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
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- staticStackSize);
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- (int) staticStackSize);
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mvec[0]->SetMachineOperand(2, target.getRegInfo().getStackPointer());
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return 1;
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@ -1122,7 +1134,7 @@ unsigned
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GetInstructionsByRule(InstructionNode* subtreeRoot,
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int ruleForNode,
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short* nts,
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TargetMachine &tgt,
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TargetMachine &target,
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MachineInstr** mvec)
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{
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int numInstr = 1; // initialize for common case
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@ -1134,8 +1146,6 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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int64_t s0=0, s8=8; // variables holding constants to avoid
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uint64_t u0=0; // overloading ambiguities below
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UltraSparc& target = (UltraSparc&) tgt;
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for (unsigned i=0; i < MAX_INSTR_PER_VMINSTR; i++)
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mvec[i] = NULL;
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@ -1266,9 +1276,9 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mvec[0] = new MachineInstr(ChooseBccInstruction(subtreeRoot,
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isFPBranch));
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Value* ccValue = isFPBranch? subtreeRoot->leftChild()->getValue()
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: GetTmpForCC(subtreeRoot->leftChild()->getValue(),
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brInst->getParent()->getParent());
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Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
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brInst->getParent()->getParent(),
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isFPBranch? Type::FloatTy : Type::IntTy);
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, ccValue);
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mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
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@ -1343,7 +1353,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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assert(0 && "VRegList should never be the topmost non-chain rule");
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break;
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case 21: // reg: Not(reg): Implemented as reg = reg XOR-NOT 0
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case 21: // bool: Not(bool): Both these are implemented as:
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case 321: // reg: BNot(reg) : reg = reg XOR-NOT 0
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mvec[0] = new MachineInstr(XNOR);
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
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subtreeRoot->leftChild()->getValue());
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@ -1408,7 +1419,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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}
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else
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{
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opType = subtreeRoot->leftChild()->getValue()->getType();
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leftVal = subtreeRoot->leftChild()->getValue();
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opType = leftVal->getType();
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MachineOpCode opCode=ChooseConvertToFloatInstr(subtreeRoot,opType);
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if (opCode == INVALID_OPCODE) // no conversion needed
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{
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@ -1417,8 +1429,42 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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}
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else
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{
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mvec[0] = new MachineInstr(opCode);
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Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
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// If the source operand is a non-FP type it must be
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// first copied from int to float register via memory!
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Instruction *dest = subtreeRoot->getInstruction();
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Value* srcForCast;
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int n = 0;
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if (opType != Type::FloatTy && opType != Type::DoubleTy)
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{
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// Create a temporary to represent the FP register
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// into which the integer will be copied via memory.
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srcForCast = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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dest, NULL);
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dest->getMachineInstrVec().addTempValue(srcForCast);
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vector<MachineInstr*> minstrVec;
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vector<TmpInstruction*> tempVec;
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target.getInstrInfo().CreateCodeToCopyIntToFloat(
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dest->getParent()->getParent(),
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leftVal, (TmpInstruction*) srcForCast,
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minstrVec, tempVec, target);
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for (unsigned i=0; i < minstrVec.size(); ++i)
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mvec[n++] = minstrVec[i];
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for (unsigned i=0; i < tempVec.size(); ++i)
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dest->getMachineInstrVec().addTempValue(tempVec[i]);
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}
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else
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srcForCast = leftVal;
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MachineInstr* castI = new MachineInstr(opCode);
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castI->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
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srcForCast);
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castI->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
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dest);
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mvec[n++] = castI;
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numInstr = n;
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}
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}
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break;
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@ -1528,35 +1574,44 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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break;
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}
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case 38: // reg: And(reg, reg)
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case 238: // reg: And(reg, Constant)
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case 38: // bool: And(bool, bool)
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case 238: // bool: And(bool, boolconst)
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case 338: // reg : BAnd(reg, reg)
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case 538: // reg : BAnd(reg, Constant)
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mvec[0] = new MachineInstr(AND);
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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case 138: // reg: And(reg, not)
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case 138: // bool: And(bool, not)
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case 438: // bool: BAnd(bool, not)
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mvec[0] = new MachineInstr(ANDN);
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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case 39: // reg: Or(reg, reg)
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case 239: // reg: Or(reg, Constant)
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case 39: // bool: Or(bool, bool)
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case 239: // bool: Or(bool, boolconst)
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case 339: // reg : BOr(reg, reg)
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case 539: // reg : BOr(reg, Constant)
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mvec[0] = new MachineInstr(ORN);
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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case 139: // reg: Or(reg, not)
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case 139: // bool: Or(bool, not)
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case 439: // bool: BOr(bool, not)
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mvec[0] = new MachineInstr(ORN);
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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case 40: // reg: Xor(reg, reg)
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case 240: // reg: Xor(reg, Constant)
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case 40: // bool: Xor(bool, bool)
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case 240: // bool: Xor(bool, boolconst)
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case 340: // reg : BXor(reg, reg)
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case 540: // reg : BXor(reg, Constant)
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mvec[0] = new MachineInstr(XOR);
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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case 140: // reg: Xor(reg, not)
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case 140: // bool: Xor(bool, not)
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case 440: // bool: BXor(bool, not)
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mvec[0] = new MachineInstr(XNOR);
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
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break;
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@ -1617,10 +1672,28 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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bool mustClearReg;
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int valueToMove;
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MachineOpCode movOpCode = 0;
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Value* ccValue = NULL;
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// Mark the 4th operand as being a CC register, and as a def
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// A TmpInstruction is created to represent the CC "result".
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// Unlike other instances of TmpInstruction, this one is used
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// by machine code of multiple LLVM instructions, viz.,
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// the SetCC and the branch. Make sure to get the same one!
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// Note that we do this even for FP CC registers even though they
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// are explicit operands, because the type of the operand
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// needs to be a floating point condition code, not an integer
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// condition code. Think of this as casting the bool result to
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// a FP condition code register.
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//
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leftVal = subtreeRoot->leftChild()->getValue();
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bool isFPCompare = (leftVal->getType() == Type::FloatTy ||
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leftVal->getType() == Type::DoubleTy);
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if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() ||
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subtreeRoot->leftChild()->getValue()->getType()->isPointerType())
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TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
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setCCInstr->getParent()->getParent(),
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isFPCompare? Type::FloatTy : Type::IntTy);
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setCCInstr->getMachineInstrVec().addTempValue(tmpForCC);
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if (! isFPCompare)
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{
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// Integer condition: dest. should be %g0 or an integer register.
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// If result must be saved but condition is not SetEQ then we need
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@ -1630,16 +1703,6 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mvec[0] = new MachineInstr(SUBcc);
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Set3OperandsFromInstr(mvec[0], subtreeRoot, target, ! keepSubVal);
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// Mark the 4th operand as being a CC register, and as a def
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// A TmpInstruction is created to represent the int CC "result".
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// Unlike other instances of TmpInstruction, this one is used by
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// used by machine code of multiple LLVM instructions, viz.,
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// the SetCC and the branch. Make sure to get the same one!
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//
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TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
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setCCInstr->getParent()->getParent());
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setCCInstr->getMachineInstrVec().addTempValue(tmpForCC);
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mvec[0]->SetMachineOperand(3, MachineOperand::MO_CCRegister,
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tmpForCC, /*def*/true);
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@ -1647,7 +1710,6 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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{ // recompute bool using the integer condition codes
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movOpCode =
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ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
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ccValue = tmpForCC;
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}
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}
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else
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@ -1655,7 +1717,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// FP condition: dest of FCMP should be some FCCn register
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mvec[0] = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
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mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
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setCCInstr);
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tmpForCC);
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mvec[0]->SetMachineOperand(1,MachineOperand::MO_VirtualRegister,
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subtreeRoot->leftChild()->getValue());
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mvec[0]->SetMachineOperand(2,MachineOperand::MO_VirtualRegister,
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@ -1666,14 +1728,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mustClearReg = true;
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valueToMove = 1;
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movOpCode = ChooseMovFpccInstruction(subtreeRoot);
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ccValue = setCCInstr;
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}
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}
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if (computeBoolVal)
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{
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assert(ccValue && "Inconsistent logic above and here");
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if (mustClearReg)
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{// Unconditionally set register to 0
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int n = numInstr++;
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@ -1688,7 +1747,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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int n = numInstr++;
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mvec[n] = new MachineInstr(movOpCode);
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mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
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ccValue);
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tmpForCC);
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mvec[n]->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
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valueToMove);
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mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
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@ -1742,12 +1801,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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assert(tsize != 0 && "Just to check when this can happen");
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Method* method = instr->getParent()->getParent();
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MachineCodeForMethod& mcode = method->getMachineCode();
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int offsetFromFP =
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target.getFrameInfo().getFirstAutomaticVarOffsetFromFP(method)
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- (tsize + mcode.getAutomaticVarsSize());
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mcode.putLocalVarAtOffsetFromFP(instr, offsetFromFP, tsize);
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MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
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int offsetFromFP = mcInfo.allocateLocalVar(target, instr);
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// Create a temporary Value to hold the constant offset.
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// This is needed because it may not fit in the immediate field.
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@ -1782,17 +1837,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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// Create a temporary Value to hold the constant offset from SP
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Method* method = instr->getParent()->getParent();
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MachineCodeForMethod& mcode = method->getMachineCode();
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int frameSizeBelowDynamicArea =
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target.getFrameInfo().getFrameSizeBelowDynamicArea(method);
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ConstPoolSInt* lowerAreaSizeVal = ConstPoolSInt::get(Type::IntTy,
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frameSizeBelowDynamicArea);
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cerr << "***" << endl
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<< "*** Variable-size ALLOCA operation needs more work:" << endl
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<< "*** We have to precompute the size of "
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<< " optional arguments in the stack frame" << endl
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<< "***" << endl;
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assert(0 && "SEE MESSAGE ABOVE");
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bool ignore; // we don't need this
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ConstPoolSInt* dynamicAreaOffset = ConstPoolSInt::get(Type::IntTy,
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target.getFrameInfo().getDynamicAreaOffset(MachineCodeForMethod::get(method),
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ignore));
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// Create a temporary value to hold `tmp'
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Instruction* tmpInstr = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
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@ -1822,7 +1870,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mvec[2] = new MachineInstr(ADD);
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mvec[2]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
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mvec[2]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
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lowerAreaSizeVal);
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dynamicAreaOffset);
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mvec[2]->SetMachineOperand(2,MachineOperand::MO_VirtualRegister,instr);
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break;
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}
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