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Clean up redundant copies of Triple objects. NFC

Browse Source 
Summary:

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10382


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239823 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2015-06-16 15:44:21 +00:00
parent 8a8bb45a76
commit ffb22b8d80
29 changed files with 54 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/AArch64/AArch64AsmPrinter.cpp
View File

@ -121,7 +121,7 @@ private:
//===----------------------------------------------------------------------===//
void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
if (TT.isOSBinFormatMachO()) {
// Funny Darwin hack: This flag tells the linker that no global symbols
// contain code that falls through to other global symbols (e.g. the obvious

2
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -2559,7 +2559,7 @@ bool AArch64TargetLowering::isEligibleForTailCallOptimization(
// cannot rely on the linker replacing the tail call with a return.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
const GlobalValue *GV = G->getGlobal();
const Triple TT(getTargetMachine().getTargetTriple());
const Triple &TT = getTargetMachine().getTargetTriple();
if (GV->hasExternalWeakLinkage() &&
(!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
return false;

14
lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -128,9 +128,9 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
bool LittleEndian)
// This nested ternary is horrible, but DL needs to be properly
// initialized before TLInfo is constructed.
: LLVMTargetMachine(T, computeDataLayout(Triple(TT), LittleEndian), TT, CPU,
FS, Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
: LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
Options, RM, CM, OL),
TLOF(createTLOF(getTargetTriple())),
isLittle(LittleEndian) {
initAsmInfo();
}
@ -155,8 +155,8 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
// creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions.
resetTargetOptions(F);
I = llvm::make_unique<AArch64Subtarget>(Triple(TargetTriple), CPU, FS,
*this, isLittle);
I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
isLittle);
}
return I.get();
}
@ -267,7 +267,7 @@ bool AArch64PassConfig::addInstSelector() {
// For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
// references to _TLS_MODULE_BASE_ as possible.
if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
if (TM->getTargetTriple().isOSBinFormatELF() &&
getOptLevel() != CodeGenOpt::None)
addPass(createAArch64CleanupLocalDynamicTLSPass());
@ -322,6 +322,6 @@ void AArch64PassConfig::addPreEmitPass() {
// range of their destination.
addPass(createAArch64BranchRelaxation());
if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
Triple(TM->getTargetTriple()).isOSBinFormatMachO())
TM->getTargetTriple().isOSBinFormatMachO())
addPass(createAArch64CollectLOHPass());
}

2
lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp
View File

@ -208,7 +208,7 @@ MCELFStreamer *createAArch64ELFStreamer(MCContext &Context, MCAsmBackend &TAB,
MCTargetStreamer *
createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
Triple TT(STI.getTargetTriple());
const Triple &TT = STI.getTargetTriple();
if (TT.getObjectFormat() == Triple::ELF)
return new AArch64TargetELFStreamer(S);
return nullptr;

6
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -429,7 +429,7 @@ void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
}
void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
// Use unified assembler syntax.
OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
@ -473,7 +473,7 @@ emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
if (TT.isOSBinFormatMachO()) {
// All darwin targets use mach-o.
const TargetLoweringObjectFileMachO &TLOFMacho =
@ -564,7 +564,7 @@ void ARMAsmPrinter::emitAttributes() {
// anyhow.
// FIXME: For ifunc related functions we could iterate over and look
// for a feature string that doesn't match the default one.
const Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
StringRef CPU = TM.getTargetCPU();
StringRef FS = TM.getTargetFeatureString();
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);

2
lib/Target/ARM/ARMAsmPrinter.h
View File

@ -105,7 +105,7 @@ private:
public:
unsigned getISAEncoding() override {
// ARM/Darwin adds ISA to the DWARF info for each function.
Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
if (!TT.isOSBinFormatMachO())
return 0;
bool isThumb = TT.getArch() == Triple::thumb ||

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -2043,7 +2043,7 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
// cannot rely on the linker replacing the tail call with a return.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
const GlobalValue *GV = G->getGlobal();
const Triple TT(getTargetMachine().getTargetTriple());
const Triple &TT = getTargetMachine().getTargetTriple();
if (GV->hasExternalWeakLinkage() &&
(!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
return false;

8
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -178,7 +178,7 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
CPU, FS, Options, RM, CM, OL),
TargetABI(computeTargetABI(TT, CPU, Options)),
TLOF(createTLOF(Triple(getTargetTriple()))),
TLOF(createTLOF(getTargetTriple())),
Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
// Default to triple-appropriate float ABI
@ -220,8 +220,7 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
// creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions.
resetTargetOptions(F);
I = llvm::make_unique<ARMSubtarget>(Triple(TargetTriple), CPU, FS, *this,
isLittle);
I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
}
return I.get();
}
@ -355,8 +354,7 @@ bool ARMPassConfig::addPreISel() {
bool ARMPassConfig::addInstSelector() {
addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
TM->Options.EnableFastISel)
if (TM->getTargetTriple().isOSBinFormatELF() && TM->Options.EnableFastISel)
addPass(createARMGlobalBaseRegPass());
return false;
}

2
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
View File

@ -1324,7 +1324,7 @@ MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S) {
MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
const MCSubtargetInfo &STI) {
Triple TT(STI.getTargetTriple());
const Triple &TT = STI.getTargetTriple();
if (TT.getObjectFormat() == Triple::ELF)
return new ARMTargetELFStreamer(S);
return new ARMTargetStreamer(S);

2
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -57,7 +57,7 @@ public:
return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
}
bool isTargetMachO(const MCSubtargetInfo &STI) const {
Triple TT(STI.getTargetTriple());
const Triple &TT = STI.getTargetTriple();
return TT.isOSBinFormatMachO();
}

6
lib/Target/BPF/BPFTargetMachine.cpp
View File

@ -41,10 +41,10 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS,
Options, RM, CM, OL),
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(Triple(TT), CPU, FS, *this) {
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}
namespace {

2
lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
View File

@ -47,7 +47,7 @@ unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
llvm_unreachable("Unhandled ABI");
}
MipsABIInfo MipsABIInfo::computeTargetABI(Triple TT, StringRef CPU,
MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) {
if (Options.getABIName().startswith("o32"))
return MipsABIInfo::O32();

2
lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
View File

@ -36,7 +36,7 @@ public:
static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); }
static MipsABIInfo computeTargetABI(Triple TT, StringRef CPU,
static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU,
const MCTargetOptions &Options);
bool IsKnown() const { return ThisABI != ABI::Unknown; }

2
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -694,7 +694,7 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
// clean anyhow.
// FIXME: For ifunc related functions we could iterate over and look
// for a feature string that doesn't match the default one.
const Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
StringRef FS = TM.getTargetFeatureString();
const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);

3
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -141,8 +141,7 @@ CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
MipsSubtarget &
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine &TM) {
std::string CPUName =
MIPS_MC::selectMipsCPU(Triple(TM.getTargetTriple()), CPU);
std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);

4
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -156,8 +156,8 @@ MipsTargetMachine::getSubtargetImpl(const Function &F) const {
// creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions.
resetTargetOptions(F);
I = llvm::make_unique<MipsSubtarget>(Triple(TargetTriple), CPU, FS,
isLittle, *this);
I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle,
*this);
}
return I.get();
}

4
lib/Target/NVPTX/NVPTXAsmPrinter.cpp
View File

@ -808,7 +808,7 @@ bool NVPTXAsmPrinter::doInitialization(Module &M) {
// Construct a default subtarget off of the TargetMachine defaults. The
// rest of NVPTX isn't friendly to change subtargets per function and
// so the default TargetMachine will have all of the options.
const Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
StringRef CPU = TM.getTargetCPU();
StringRef FS = TM.getTargetFeatureString();
const NVPTXTargetMachine &NTM = static_cast<const NVPTXTargetMachine &>(TM);
@ -846,7 +846,7 @@ bool NVPTXAsmPrinter::doInitialization(Module &M) {
}
// If we're not NVCL we're CUDA, go ahead and emit filenames.
if (Triple(TM.getTargetTriple()).getOS() != Triple::NVCL)
if (TM.getTargetTriple().getOS() != Triple::NVCL)
recordAndEmitFilenames(M);
GlobalsEmitted = false;

2
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
View File

@ -309,7 +309,7 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
// Return the thread-pointer register's encoding.
Fixups.push_back(MCFixup::create(0, MO.getExpr(),
(MCFixupKind)PPC::fixup_ppc_nofixup));
Triple TT(STI.getTargetTriple());
const Triple &TT = STI.getTargetTriple();
bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le;
return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2);
}

2
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -230,7 +230,7 @@ static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
static MCTargetStreamer *
createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
Triple TT(STI.getTargetTriple());
const Triple &TT = STI.getTargetTriple();
if (TT.getObjectFormat() == Triple::ELF)
return new PPCTargetELFStreamer(S);
return new PPCTargetMachOStreamer(S);

4
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -440,7 +440,7 @@ void PPCAsmPrinter::EmitTlsCall(const MachineInstr *MI,
void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst TmpInst;
bool isPPC64 = Subtarget->isPPC64();
bool isDarwin = Triple(TM.getTargetTriple()).isOSDarwin();
bool isDarwin = TM.getTargetTriple().isOSDarwin();
const Module *M = MF->getFunction()->getParent();
PICLevel::Level PL = M->getPICLevel();
@ -1511,7 +1511,7 @@ bool PPCDarwinAsmPrinter::doFinalization(Module &M) {
static AsmPrinter *
createPPCAsmPrinterPass(TargetMachine &tm,
std::unique_ptr<MCStreamer> &&Streamer) {
if (Triple(tm.getTargetTriple()).isMacOSX())
if (tm.getTargetTriple().isMacOSX())
return new PPCDarwinAsmPrinter(tm, std::move(Streamer));
return new PPCLinuxAsmPrinter(tm, std::move(Streamer));
}

4
lib/Target/PowerPC/PPCCTRLoops.cpp
View File

@ -417,8 +417,8 @@ bool PPCCTRLoops::mightUseCTR(const Triple &TT, BasicBlock *BB) {
bool PPCCTRLoops::convertToCTRLoop(Loop *L) {
bool MadeChange = false;
Triple TT = Triple(L->getHeader()->getParent()->getParent()->
getTargetTriple());
const Triple TT =
Triple(L->getHeader()->getParent()->getParent()->getTargetTriple());
if (!TT.isArch32Bit() && !TT.isArch64Bit())
return MadeChange; // Unknown arch. type.

2
lib/Target/PowerPC/PPCMCInstLower.cpp
View File

@ -40,7 +40,7 @@ static MCSymbol *GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP){
Mangler *Mang = AP.Mang;
const DataLayout *DL = TM.getDataLayout();
MCContext &Ctx = AP.OutContext;
bool isDarwin = Triple(TM.getTargetTriple()).isOSDarwin();
bool isDarwin = TM.getTargetTriple().isOSDarwin();
SmallString<128> Name;
StringRef Suffix;

11
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -171,7 +171,7 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
TLOF(createTLOF(getTargetTriple())),
TargetABI(computeTargetABI(TT, Options)) {
initAsmInfo();
}
@ -215,7 +215,7 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
// function that reside in TargetOptions.
resetTargetOptions(F);
I = llvm::make_unique<PPCSubtarget>(
Triple(TargetTriple), CPU,
TargetTriple, CPU,
// FIXME: It would be good to have the subtarget additions here
// not necessary. Anything that turns them on/off (overrides) ends
// up being put at the end of the feature string, but the defaults
@ -262,9 +262,8 @@ void PPCPassConfig::addIRPasses() {
// For the BG/Q (or if explicitly requested), add explicit data prefetch
// intrinsics.
bool UsePrefetching =
Triple(TM->getTargetTriple()).getVendor() == Triple::BGQ &&
getOptLevel() != CodeGenOpt::None;
bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
getOptLevel() != CodeGenOpt::None;
if (EnablePrefetch.getNumOccurrences() > 0)
UsePrefetching = EnablePrefetch;
if (UsePrefetching)
@ -318,7 +317,7 @@ void PPCPassConfig::addMachineSSAOptimization() {
TargetPassConfig::addMachineSSAOptimization();
// For little endian, remove where possible the vector swap instructions
// introduced at code generation to normalize vector element order.
if (Triple(TM->getTargetTriple()).getArch() == Triple::ppc64le &&
if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
!DisableVSXSwapRemoval)
addPass(createPPCVSXSwapRemovalPass());
}

2
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -50,7 +50,7 @@ public:
}
bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
bool isPPC64() const {
Triple TT(getTargetTriple());
const Triple &TT = getTargetTriple();
return (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
};
};

2
lib/Target/TargetLoweringObjectFile.cpp
View File

@ -44,7 +44,7 @@ void TargetLoweringObjectFile::Initialize(MCContext &ctx,
const TargetMachine &TM) {
Ctx = &ctx;
DL = TM.getDataLayout();
InitMCObjectFileInfo(Triple(TM.getTargetTriple()), TM.getRelocationModel(),
InitMCObjectFileInfo(TM.getTargetTriple(), TM.getRelocationModel(),
TM.getCodeModel(), *Ctx);
}

2
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -54,7 +54,7 @@ std::string X86_MC::ParseX86Triple(const Triple &TT) {
return FS;
}
unsigned X86_MC::getDwarfRegFlavour(Triple TT, bool isEH) {
unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
if (TT.getArch() == Triple::x86_64)
return DWARFFlavour::X86_64;

2
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
View File

@ -54,7 +54,7 @@ namespace N86 {
namespace X86_MC {
std::string ParseX86Triple(const Triple &TT);
unsigned getDwarfRegFlavour(Triple TT, bool isEH);
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);

6
lib/Target/X86/X86AsmPrinter.cpp
View File

@ -511,7 +511,7 @@ bool X86AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
}
void X86AsmPrinter::EmitStartOfAsmFile(Module &M) {
Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
if (TT.isOSBinFormatMachO())
OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
@ -585,7 +585,7 @@ void X86AsmPrinter::GenerateExportDirective(const MCSymbol *Sym, bool IsData) {
SmallString<128> Directive;
raw_svector_ostream OS(Directive);
StringRef Name = Sym->getName();
Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
if (TT.isKnownWindowsMSVCEnvironment())
OS << " /EXPORT:";
@ -610,7 +610,7 @@ void X86AsmPrinter::GenerateExportDirective(const MCSymbol *Sym, bool IsData) {
}
void X86AsmPrinter::EmitEndOfAsmFile(Module &M) {
Triple TT(TM.getTargetTriple());
const Triple &TT = TM.getTargetTriple();
if (TT.isOSBinFormatMachO()) {
// All darwin targets use mach-o.

8
lib/Target/X86/X86TargetMachine.cpp
View File

@ -101,7 +101,7 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
OL),
TLOF(createTLOF(Triple(getTargetTriple()))),
TLOF(createTLOF(getTargetTriple())),
Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
// Windows stack unwinder gets confused when execution flow "falls through"
// after a call to 'noreturn' function.
@ -153,7 +153,7 @@ X86TargetMachine::getSubtargetImpl(const Function &F) const {
// creation will depend on the TM and the code generation flags on the
// function that reside in TargetOptions.
resetTargetOptions(F);
I = llvm::make_unique<X86Subtarget>(Triple(TargetTriple), CPU, FS, *this,
I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
Options.StackAlignmentOverride);
}
return I.get();
@ -218,7 +218,7 @@ bool X86PassConfig::addInstSelector() {
addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
// For ELF, cleanup any local-dynamic TLS accesses.
if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
if (TM->getTargetTriple().isOSBinFormatELF() &&
getOptLevel() != CodeGenOpt::None)
addPass(createCleanupLocalDynamicTLSPass());
@ -236,7 +236,7 @@ bool X86PassConfig::addILPOpts() {
bool X86PassConfig::addPreISel() {
// Only add this pass for 32-bit x86 Windows.
Triple TT(TM->getTargetTriple());
const Triple &TT = TM->getTargetTriple();
if (TT.isOSWindows() && TT.getArch() == Triple::x86)
addPass(createX86WinEHStatePass());
return true;