5341 Commits

Author SHA1 Message Date
Krzysztof Parzyszek
60719d620c [Hexagon] Fix disassembler crash after r279255
When p0 was added as an explicit operand to the duplex subinstructions,
the disassembler was not updated to reflect this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281104 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-09 21:45:00 +00:00
Wei Ding
8dae05acf4 AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type.
Differential Revision: http://reviews.llvm.org/D23700

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281081 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-09 19:31:51 +00:00
Sam Kolton
03d317688d AMDGPU] Assembler: better support for immediate literals in assembler.
Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.

With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
    - We parsed fp literal:
        - Instruction expects 64-bit operand:
            - If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
                - then we do nothing this literal
            - Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
                - report error
            - Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
                - If instruction expect fp operand type (f64)
                    - Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
                        - If so then do nothing
                    - Else (e.g. v_fract_f64 v[0:1], 3.1415)
                        - report warning that low 32 bits will be set to zeroes and precision will be lost
                        - set low 32 bits of literal to zeroes
                - Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
                    - report error as it is unclear how to encode this literal
        - Instruction expects 32-bit operand:
            - Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
            - Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
                - do nothing
                - Else report error
            - Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
    - Parsed binary literal:
        - Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
            - do nothing
        - Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
            - report error
        - Else, literal is not-inlinable and we are not required to inline it
            - Are high 32 bit of literal zeroes or same as sign bit (32 bit)
                - do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
            - Else
                - report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)

For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
    OPERAND_REG_IMM32_INT,
    OPERAND_REG_IMM32_FP,
    OPERAND_REG_INLINE_C_INT,
    OPERAND_REG_INLINE_C_FP,
}
'''

This is not working yet:
    - Several tests are failing
    - Problems with predicate methods for inline immediates
    - LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.

Reviewers: vpykhtin, tstellarAMD

Subscribers: arsenm, kzhuravl, artem.tamazov

Differential Revision: https://reviews.llvm.org/D22922

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281050 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-09 14:44:04 +00:00
Simon Dardis
80f518b791 Revert "[mips] Fix c.<cc>.<fmt> instruction definition."
This reverts commit r281022. Mips buildbot broke, due to unhandled register
class FCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281033 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-09 11:06:01 +00:00
Sam Kolton
442deaa85b [AMDGPU] Assembler: rename amd_kernel_code_t asm names according to spec
Summary:
Also removed duplicate code from AMDGPUTargetAsmStreamer.
This change only change how amd_kernel_code_t is parsed and printed. No variable names are changed.

Reviewers: vpykhtin, tstellarAMD

Subscribers: arsenm, wdng, nhaehnle

Differential Revision: https://reviews.llvm.org/D24296

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281028 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-09 10:08:02 +00:00
Simon Dardis
43cc6f8676 [mips] Fix c.<cc>.<fmt> instruction definition.
As part of this effort, remove MipsFCmp nodes and use tablegen
patterns rather than custom lowering through C++.

Unexpectedly, this improves codesize for microMIPS as previous floating
point setcc expansions would materialize 0 and 1 into GPRs before using
the relevant mov[tf].[sd] instruction. Now $zero is used directly.

Reviewers: dsanders, vkalintiris, zoran.jovanovic

Differential Review: https://reviews.llvm.org/D23118


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281022 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-09 09:22:52 +00:00
Eric Christopher
a50ca9fdb6 AArch64 .arch directive - Include default arch attributes with extensions.
Fix the .arch asm parser to use the full set of features for the architecture
and any extensions on the command line. Add and update testcases accordingly
as well as add an extension that was used but not supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280971 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-08 17:27:03 +00:00
Reid Kleckner
1a53e071f4 Give an x86 assembler test a triple
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280950 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-08 15:40:43 +00:00
Hrvoje Varga
09e92562f1 [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI instructions
Differential Revision: https://reviews.llvm.org/D16452


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280909 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-08 07:41:43 +00:00
Reid Kleckner
eadc14fcd6 [codeview] Add new directives to record inlined call site line info
Summary:
Previously we were trying to represent this with the "contains" list of
the .cv_inline_linetable directive, which was not enough information.
Now we directly represent the chain of inlined call sites, so we know
what location to emit when we encounter a .cv_loc directive of an inner
inlined call site while emitting the line table of an outer function or
inlined call site. Fixes PR29146.

Also fixes PR29147, where we would crash when .cv_loc directives crossed
sections. Now we write down the section of the first .cv_loc directive,
and emit an error if any other .cv_loc directive for that function is in
a different section.

Also fixes issues with discontiguous inlined source locations, like in
this example:

  volatile int unlikely_cond = 0;
  extern void __declspec(noreturn) abort();
  __forceinline void f() {
    if (!unlikely_cond) abort();
  }
  int main() {
    unlikely_cond = 0;
    f();
    unlikely_cond = 0;
  }

Previously our tables gave bad location information for the 'abort'
call, and the debugger wouldn't snow the inlined stack frame for 'f'.
It is important to emit good line tables for this code pattern, because
it comes up whenever an asan bug occurs in an inlined function. The
__asan_report* stubs are generally placed after the normal function
epilogue, leading to discontiguous regions of inlined code.

Reviewers: majnemer, amccarth

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24014

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280822 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-07 16:15:31 +00:00
James Molloy
af86df2b0f [Thumb1] Add relocations for fixups fixup_arm_thumb_{br,bcc}
These need to be mapped through to R_ARM_THM_JUMP{11,8} respectively.

Fixes PR30279.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280651 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-05 08:29:15 +00:00
Hal Finkel
f86e7eec65 [PowerPC] Support asm parsing for bc[l][a][+-] mnemonics
PowerPC assembly code in the wild, so it seems, has things like this:

  bc+     12, 28, .L9

This is a bit odd because the '+' here becomes part of the BO field, and the BO
field is otherwise the first operand. Nevertheless, the ISA specification does
clearly say that the +- hint syntax applies to all conditional-branch mnemonics
(that test either CTR or a condition register, although not the forms which
check both), both basic and extended, so this is supposed to be valid.

This introduces some asm-parser-only definitions which take only the upper
three bits from the specified BO value, and the lower two bits are implied by
the +- suffix (via some associated aliases).

Fixes PR23646.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280571 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-03 02:31:44 +00:00
Hal Finkel
1211eb07d5 [PowerPC] Add asm parser/disassembler support for hrfid,nap,slbmfev
These few book-III instructions are used by the Linux kernel.

Partially fixes PR24796.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280560 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-02 23:42:01 +00:00
Hal Finkel
fe681a8119 [PowerPC] Add support for the extended dcbf form and mnemonics
dcbf has an optional hint-like field, add support for the extended form and the
associated mnemonics (dcbfl and dcbflp).

Partially fixes PR24796.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280559 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-02 23:41:54 +00:00
James Molloy
f37c8a6b19 [SimplifyCFG] Handle tail-sinking of more than 2 incoming branches
This was a real restriction in the original version of SinkIfThenCodeToEnd. Now it's been rewritten, the restriction can be lifted.

As part of this, we handle a very common and useful case where one of the incoming branches is actually conditional. Consider:

   if (a)
     x(1);
   else if (b)
     x(2);

This produces the following CFG:

         [if]
        /    \
      [x(1)] [if]
        |     | \
        |     |  \
        |  [x(2)] |
         \    |  /
          [ end ]

[end] has two unconditional predecessor arcs and one conditional. The conditional refers to the implicit empty 'else' arc. This same pattern can also be caused by an empty default block in a switch.

We can't sink the call to x() down to end because no call to x() happens on the third incoming arc (assume that x() has sideeffects for the sake of argument; if something is safe to speculate we could indeed sink nevertheless but this cannot happen in the general case and causes many extra selects).

We are now able to detect this case and split off the unconditional arcs to a common successor:

         [if]
        /    \
      [x(1)] [if]
        |     | \
        |     |  \
        |  [x(2)] |
         \   /    |
     [sink.split] |
           \     /
           [ end ]

Now we can sink the call to x() into %sink.split. This can cause significant code simplification in many testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280364 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-01 12:58:13 +00:00
James Molloy
85dac9a06d Revert "[SimplifyCFG] Handle tail-sinking of more than 2 incoming branches"
This reverts commit r280217. r280216 caused buildbot failures - backing out the entire chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280233 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-31 13:16:45 +00:00
James Molloy
e786823705 [SimplifyCFG] Handle tail-sinking of more than 2 incoming branches
This was a real restriction in the original version of SinkIfThenCodeToEnd. Now it's been rewritten, the restriction can be lifted.

As part of this, we handle a very common and useful case where one of the incoming branches is actually conditional. Consider:

   if (a)
     x(1);
   else if (b)
     x(2);

This produces the following CFG:

         [if]
        /    \
      [x(1)] [if]
        |     | \
        |     |  \
        |  [x(2)] |
         \    |  /
          [ end ]

[end] has two unconditional predecessor arcs and one conditional. The conditional refers to the implicit empty 'else' arc. This same pattern can also be caused by an empty default block in a switch.

We can't sink the call to x() down to end because no call to x() happens on the third incoming arc (assume that x() has sideeffects for the sake of argument; if something is safe to speculate we could indeed sink nevertheless but this cannot happen in the general case and causes many extra selects).

We are now able to detect this case and split off the unconditional arcs to a common successor:

         [if]
        /    \
      [x(1)] [if]
        |     | \
        |     |  \
        |  [x(2)] |
         \   /    |
     [sink.split] |
           \     /
           [ end ]

Now we can sink the call to x() into %sink.split. This can cause significant code simplification in many testcases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280217 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-31 10:46:33 +00:00
Craig Topper
8b5392fd41 [X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test for CR8-CR15.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279921 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 17:13:34 +00:00
Matt Arsenault
d97fe48fe0 AMDGPU: Improve error reporting for maximum branch distance
Unfortunately this seems to only help the assembler diagnostic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279895 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-27 00:21:22 +00:00
Tim Northover
6361cd131c ARM: by default don't set the Thumb bit on MachO relocated values.
Its existence is largely historical, apparently we tried to make ARM object
files look maybe-almost-possibly runnable by putting our best guess at the
actual value into relocated locations. Of course, the real linker then comes
along and can completely change things.

But it should only be there for word-sized and movw/movt relocations. It can't
be encoded in branch relocations, and I've seen it mess up validity
calculations twice in the last couple of weeks so the default is clearly problematic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279773 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-25 20:41:30 +00:00
Tim Northover
b55d189bbc ARM: don't diagnose cbz/cbnz to Thumb functions.
A branch-distance to a Thumb function shouldn't be forced to be odd for
CBZ/CBNZ instructions because (assuming it's within range), it's going to be a
valid, even offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279665 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-24 21:21:29 +00:00
Petr Hosek
e994d796e2 [MC] Support .dc directives in assembler parser
While these directives are mostly aliases for the existing integer
and float value directives, some of them like .dc.a have no direct
equivalents and are sometimes being used for convenience.

Differential Revision: https://reviews.llvm.org/D23810

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279577 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-23 21:34:53 +00:00
Simon Atanasyan
b469a386bb [mips][ias] Support .dtprel[d]word and .tprel[d]word directives
Assembler directives .dtprelword, .dtpreldword, .tprelword, and
.tpreldword generates relocations R_MIPS_TLS_DTPREL32, R_MIPS_TLS_DTPREL64,
R_MIPS_TLS_TPREL32, and R_MIPS_TLS_TPREL64 respectively.

The main motivation for this patch is to be able to write test cases
for checking correctness of the LLD linker's behaviour.

Differential Revision: https://reviews.llvm.org/D23669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279439 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-22 16:18:42 +00:00
Hrvoje Varga
00748f49d4 [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations
Differential Revision: https://reviews.llvm.org/D22667


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279429 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-22 12:17:59 +00:00
Simon Dardis
0ca6dc4466 [mips] Add l.[sd] and s.[sd] instruction aliases
Reviewers: dsanders, vkalintiris

Differential Review: https://reviews.llvm.org/D23121


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278930 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-17 14:45:09 +00:00
Prakhar Bahuguna
7461b8a6d7 Correct the upper bound for a CBZ/CBNZ branch target.
Summary:
Fix for the upper bound check that was causing a build failure.

Reviewers: olista01, rengolin, t.p.northover

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23501

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278789 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-16 10:41:56 +00:00
Prakhar Bahuguna
6e45500a57 [Thumb] Validate branch target for CBZ/CBNZ instructions.
Summary:
The assembler currently does not check the branch target for CBZ/CBNZ
instructions, which only permit branching forwards with a positive offset. This
adds validation for the branch target to ensure negative PC-relative offsets are
not encoded into the instruction, whether specified as a literal or as an
assembler symbol.

Reviewers: rengolin, t.p.northover

Subscribers: llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D23312

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278788 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-16 10:41:52 +00:00
Matthias Braun
1741b5a541 Revert "[Thumb] Validate branch target for CBZ/CBNZ instructions."
This currently breaks the greendragon clang-stage1-configure-RA/ and
brotli. It is probably just uncovering a pre-existing problem. Reverting
temporarily to get the buildbots green again. A reduced testcase will
follow shortly.

This reverts commit r278659.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278711 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-15 18:50:13 +00:00
Valery Pykhtin
9364829511 [AMDGPU] fix failure on printing of non-existing instruction operands.
Differential revision: https://reviews.llvm.org/D23323

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278665 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-15 10:56:48 +00:00
Prakhar Bahuguna
91c19fbe6c [Thumb] Validate branch target for CBZ/CBNZ instructions.
Summary:
The assembler currently does not check the branch target for CBZ/CBNZ
instructions, which only permit branching forwards with a positive offset. This
adds validation for the branch target to ensure negative PC-relative offsets are
not encoded into the instruction, whether specified as a literal or as an
assembler symbol.

Reviewers: rengolin, t.p.northover

Subscribers: llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D23312

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278659 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-15 07:57:44 +00:00
Valery Pykhtin
d27913ee68 Revert "[AMDGPU] fix failure on printing of non-existing instruction operands."
This reverts revision 278333, newly added test failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278336 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 14:22:05 +00:00
Valery Pykhtin
3876e2e984 [AMDGPU] fix failure on printing of non-existing instruction operands.
Differential revision: https://reviews.llvm.org/D23323

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278333 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 13:49:46 +00:00
Nirav Dave
cf83621dcd [X86] Improve code size on X86 segment moves
Moves of a value to a segment register from a 16-bit register is
equivalent to one from it's corresponding 32-bit register. Match gas's
behavior and rewrite instructions to the shorter of equivalent forms.

Reviewers: rnk, ab

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23166

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278031 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-08 18:01:04 +00:00
Zhan Jun Liau
c6b5e8816e [SystemZ] Add support for the .insn directive
Summary:
Add support for the .insn directive.

.insn is an s390 specific directive that allows encoding of an instruction
instead of using a mnemonic. The motivating case is some code in node.js that
requires support for the .insn directive.

Reviewers: koriakin, uweigand

Subscribers: koriakin, llvm-commits

Differential Revision: https://reviews.llvm.org/D21809

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278012 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-08 15:13:08 +00:00
Daniel Sanders
7dd6fd6b28 Re-commit r277988: [mips][ias] Fix all the hacks related to MIPS-specific unary operators (%hi/%lo/%gp_rel/etc.).
Hopefully with the MSVC builds fixed. I've added a missing '#include <tuple>'
that gcc and clang don't seem to need.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277995 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-08 11:50:25 +00:00
Daniel Sanders
0985f50be7 Revert r277988: [mips][ias] Fix all the hacks related to MIPS-specific unary operators (%hi/%lo/%gp_rel/etc.).
It seems that MSVC doesn't like std::tie().



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277990 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-08 09:33:14 +00:00
Daniel Sanders
007417372d [mips][ias] Fix all the hacks related to MIPS-specific unary operators (%hi/%lo/%gp_rel/etc.).
Summary:
They are now lexed as a single token on targets where
MCAsmInfo::HasMipsExpressions is true and then parsed in a similar way to
the '~' operator as part of MCExpr::parseExpression.

As a result:
* expressions and immediates no longer have different parsing rules. The
  difference is now solely down to whether evaluateAsAbsolute() succeeds.
* %hi(%neg(%gp_rel(x))) are no longer parsed as a single operator and
  decomposed into the three MipsMCExpr nodes. They are parsed directly as
  three MipsMCExpr nodes.
  * parseMemOperand no longer needs to eat all the surrounding parenthesis
    to get at the outermost operator to make this work
* %hi(%neg(%gp_rel(x))) and %lo(%neg(%gp_rel(x))) are no longer the only
  3-in-1 relocs that parse for N64. They're still the only combinations that
  are permitted in relocatable expressions though. Fixing that should be a
  later patch.
* We no longer need to list all the tokens that can occur as the first token of
  an expression or immediate.

test/MC/Mips/expr1.s:
    This change also prevents the incorrect lowering of %lo(2*4)+foo to
    %lo(8+foo) which is not an equivalent expression (the difference is
    whether foo is truncated to 16-bit or not) and the test has been
    updated to account for the macro expansion the correct expression requires.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: https://reviews.llvm.org/D23110

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277988 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-08 09:20:52 +00:00
Zhan Jun Liau
348f66dd36 [SystemZ] Add missing classes and instructions
Summary:
Add instruction formats E, RSI, SSd, SSE, and SSF.

Added BRXH, BRXLE, PR, MVCK, STRAG, and ECTG instructions to test out
those formats.

Reviewers: uweigand

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23179

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277822 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-05 15:14:34 +00:00
Hrvoje Varga
d2c97748ac [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructions
Differential Revision: https://reviews.llvm.org/D22347


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277719 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-04 11:22:52 +00:00
Igor Breger
48f2d1dea0 [AVX512] Add aliases for vcvttss2si{l|q}, vcvttsd2si{l|q}, vcvttss2usi{l|q}, vcvttsd2usi{l|q} instructions.
Differential Revision: http://reviews.llvm.org/D23111

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277586 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-03 10:58:05 +00:00
Nirav Dave
0fa8922515 Fix handling of end-of-line preprocessor comments Attempt 2
Attempt 2: Retryign after Tsan.mman test fix.

Attempt 1: Recommitting after fixing test.

When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.

Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.

Reviewers: rnk, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277501 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:17:54 +00:00
Nirav Dave
c37e7b92f8 [MC] Fix Intel Operand assembly parsing for .set ids
Recommitting after fixing overaggressive fastpath return in parsing.

Fix intel syntax special case identifier operands that refer to a constant
(e.g. .set <ID> n) to be interpreted as immediate not memory in parsing.

Associated commit to fix clang test commited shortly.

Reviewers: rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D22585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277489 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 17:56:03 +00:00
Nirav Dave
07d957665f Revert "[MC] Fix handling of end-of-line preprocessor comments"
Causes TSan failure on PPC64

This reverts commit r277459.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277468 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 15:08:52 +00:00
Nirav Dave
22973d396c [MC] Fix handling of end-of-line preprocessor comments
Recommitting after fixing test.

When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.

Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.

Reviewers: rnk, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277459 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 14:25:49 +00:00
Bruno Cardoso Lopes
b1fa8fe727 Revert r277408 and r277407
Revert r277408 "Fix test from rL277407."
Revert r277407 "[MC] Fix handling of end-of-line preprocessor comments"

This is currently breaking:
  http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/20731

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277412 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 02:53:59 +00:00
Nirav Dave
e9cc165371 Fix test from rL277407.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277408 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 01:27:09 +00:00
Nirav Dave
6fc4119b60 [MC] Fix handling of end-of-line preprocessor comments
Summary:
When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.

Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.

Reviewers: rnk, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277407 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 01:05:29 +00:00
Hans Wennborg
0e6a15a292 Revert r276895 "[MC][X86] Fix Intel Operand assembly parsing for .set ids"
This caused PR28805. Adding a regression test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277402 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 23:00:01 +00:00
Nirav Dave
b1a08aee35 Add removed inline-assembly-comment test from r277146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277349 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 15:36:10 +00:00
Valery Pykhtin
1704eb6864 [AMDGPU] refactor DS instruction definitions. NFC.
Differential revision: https://reviews.llvm.org/D22522

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277344 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-01 14:21:30 +00:00