88317 Commits

Author SHA1 Message Date
Kyle Butt
03d7c088c2 Codegen: [PPC] Word Rotates are Zero Extending.
Add Word rotates to the list of instructions that are zero extending.
This allows them to be used in dot form to compare with zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264183 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 19:51:22 +00:00
George Burgess IV
0a451a3606 Fix bugs in the MemorySSA walker.
There are a few bugs in the walker that this patch addresses.
Primarily:
- Caching can break when we have multiple BBs without phis
- We weren't optimizing some phis properly
- Because of how the DFS iterator works, there were times where we
  wouldn't cache any results of our DFS

I left the test cases with FIXMEs in, because I'm not sure how much
effort it will take to get those to work (read: We'll probably
ultimately have to end up redoing the walker, or we'll have to come up
with some creative caching tricks), and more test coverage = better.

Differential Revision: http://reviews.llvm.org/D18065


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264180 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 18:31:55 +00:00
Easwaran Raman
e34db46356 Add getBlockProfileCount method to BlockFrequencyInfo
Differential Revision: http://reviews.llvm.org/D18233



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264179 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 18:18:26 +00:00
Justin Bogner
6b4391cd9c SelectionDAG: Remove a tautological dyn_cast. NFC
Index is already a StoreSDNode, so this dyn_cast doesn't do anything.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264177 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 18:15:33 +00:00
Artyom Skrobov
2d2221d7fb Replace a string comparison in ARMSubtarget.h with a tablegen entry in ARM.td (NFC)
Reviewers: rengolin, t.p.northover

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D18393

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264165 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 16:18:13 +00:00
Silviu Baranga
0905413218 [SCEV] Change the SCEV Predicates interfaces for conversion to AddRecExpr to return SCEVAddRecExpr* instead of SCEV*
Summary:
This changes the conversion functions from SCEV * to SCEVAddRecExpr from
ScalarEvolution and PredicatedScalarEvolution to return a SCEVAddRecExpr*
instead of a SCEV* (which removes the need of most clients to do a
dyn_cast right after calling these functions).

We also don't add new predicates if the transformation was not successful.

This is not entirely a NFC (as it can theoretically remove some predicates
from LAA when we have an unknown dependece), but I couldn't find an obvious
regression test for it.

Reviewers: sanjoy

Subscribers: sanjoy, mzolotukhin, llvm-commits

Differential Revision: http://reviews.llvm.org/D18368

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264161 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 15:29:30 +00:00
Oliver Stannard
67240a7684 [AArch64] Replace some uses of report_fatal_error with reportError in AArch64 ELF object writer
If we can't handle a relocation type, report it as an error in the source,
rather than asserting. I've added a more descriptive message and a test for the
only cases of this that I've been able to trigger.

Differential Revision: http://reviews.llvm.org/D18388



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264156 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 13:45:03 +00:00
Andrey Turetskiy
2228d07bc0 [X86] Introduction of FeatureX87.
Add FeatureX87 in X86 backend to be able to define CPUs which doesn't have x87.

Differential Revision: http://reviews.llvm.org/D13979



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264148 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 11:13:54 +00:00
Hrvoje Varga
e7adbcc7a2 [mips][microMIPS] Delay slot filler modifications
Differential Revision: http://reviews.llvm.org/D18181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264147 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 10:29:38 +00:00
Valery Pykhtin
7c2672b778 [AMDGPU] Fix missing assembler predicates.
Differential Revision: http://reviews.llvm.org/D18351

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264137 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 04:27:26 +00:00
Sanjoy Das
ab71fdec0a Remove stale comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264131 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 02:28:35 +00:00
Sanjoy Das
613b7c3337 [StatepointLowering] Don't do two DenseMap lookups; nfci
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264130 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 02:24:15 +00:00
Sanjoy Das
df46390b38 [StatepointLowering] Minor NFC cleanups
- Use auto
 - Name variables in LLVM style
 - Use llvm::find instead of std::find
 - Blank lines between declarations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264129 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 02:24:13 +00:00
Sanjoy Das
0479e1aad2 [StatepointLowering] Minor nfc refactoring
Now that StatepointLoweringInfo represents base pointers, derived
pointers and gc relocates as SmallVectors and not ArrayRefs, we no
longer need to allocate "backing storage" on stack in LowerStatepoint.
So elide the backing storage, and inline the trivial body of
getIncomingStatepointGCValues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264128 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 02:24:10 +00:00
Sanjoy Das
5fb8106b47 [StatepointLowering] Schedule gc relocates before uniqueing them
Otherwise we can see an "unexpected" gc.relocate that we uniqued away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264127 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 02:24:07 +00:00
Tom Stellard
835c01151e AMDGPU: Cache information about register pressure sets
We can statically decide whether or not a register pressure set is for
SGPRs or VGPRs, so we don't need to re-compute this information in
SIRegisterInfo::getRegPressureSetLimit().

Differential Revision: http://reviews.llvm.org/D14805

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264126 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 01:53:22 +00:00
Junmo Park
1da710de1f Minor code cleanup. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264124 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 01:38:35 +00:00
Davide Italiano
11e71d65b2 [ModuleUtils] Use range-based loop. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264122 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 00:43:35 +00:00
Joerg Sonnenberger
c8740297ca Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264110 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 22:24:52 +00:00
Justin Bogner
6d476e60b2 MC: Don't access the filesystem in MCContext's constructor
MCContext shouldn't be accessing the filesystem - that's a gross
layering violation and makes it awkward to use as a library or in a
daemon where it may not even be allowed filesystem access.

The CWD lookup here is normally redundant anyway, since the calling
context either also looks up the CWD or sets this to something more
specific. Here, we fix up the one caller that doesn't already set up a
debug compilation dir and make it clear that the responsibility for
such set up is in the users of MCContext.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264109 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 22:24:29 +00:00
Rafael Espindola
a8fd65832a Drop comdats from the dst module if they are not selected.
A really unfortunate design of llvm-link and related libraries is that
they operate one module at a time.

This means they can copy a GV to the destination module that should not
be there in the final result because a later bitcode file takes
precedence.

We already handled cases like a strong GV replacing a weak for example.

One case that is not currently handled is a comdat replacing another.
This doesn't happen in ELF, but with COFF largest selection kind it is
possible.

In "llvm-link a.ll b.ll" if the selected comdat was from a.ll,
everything will work and we will not copy the comdat from b.ll.

But if we run "llvm-link b.ll a.ll", we fail to delete the already
copied comdat from b.ll. This patch fixes that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264103 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 21:35:47 +00:00
George Burgess IV
58cad7988f Keep CodeGenPrepare from preserving the domtree.
CGP modifies the domtree in some cases, so saying that it preserves the
domtree is a lie. We'll be able to selectively preserve it with the new
pass manager.

Differential Revision: http://reviews.llvm.org/D16893


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264099 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 21:25:08 +00:00
Matthias Braun
a31e891389 Revert "Support arbitrary addrspace pointers in masked load/store intrinsics"
This commit broke LTO builds. Reverting it to unbreak the bots while the
issue is investigated. See also:

http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160321/341002.html

This reverts r263158

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264088 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 20:24:34 +00:00
Simon Pilgrim
4ec7162ead [SelectionDAG] Ensure constant folded legalized vector element types are compatible with the BUILD_VECTOR type
Found during fuzz testing - 32-bit x86 targets were legalizing a <2 x i1> compare result to <2 x i32> when <2 x i64> was expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264085 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 19:59:53 +00:00
Tim Northover
7561ec8b4b CodeGen: check return types match when emitting tail call to builtin.
We were just completely ignoring the types when determining whether we could
safely emit a libcall as a tail call. This is clearly wrong.

Theoretically, we could dig deeper looking for incidental matches (much like
the generic code in Analysis.cpp does), but it's probably not worth it for the
few libcalls that exist.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264084 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 19:14:38 +00:00
Adam Nemet
0645f68799 [LoopVersioning] Relax an assert for LCSSA PHIs
When you have multiple LCSSA (single-operand) PHIs that are converted
into two-operand PHIs due to versioning, only assert that the PHI
currently being converted has a single operand.  I.e. we don't want to
check PHIs that were converted earlier in the loop.

Fixes PR27023.

Thanks to Karl-Johan Karlsson for the minimized testcase!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264081 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 18:38:15 +00:00
Sanjoy Das
340dafa6bd Allow lowering call sites with both funclets and deopt state
Lowering funclets is a no-op, so we can just go ahead and lower the
deopt state.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264078 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 18:10:39 +00:00
Dan Gohman
35d7235fd8 [WebAssembly] Implement the rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264076 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 18:01:49 +00:00
Sanjoy Das
0a4f1f9b9d Add a hasOperandBundlesOtherThan helper, and use it; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264072 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 17:51:25 +00:00
Simon Pilgrim
67edb4c4ef [X86][SSE] Reapplied: Simplify vector LOAD + EXTEND on pre-SSE41 hardware
Improve vector extension of vectors on hardware without dedicated VSEXT/VZEXT instructions.

We already convert these to SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG but can further improve this by using the legalizer instead of prematurely splitting into legal vectors in the combine as this only properly helps for lowering to VSEXT/VZEXT.

Removes a lot of unnecessary any_extend + mask pattern - (Fix for PR25718).

Reapplied with a fix for PR26953 (missing vector widening legalization).

Differential Revision: http://reviews.llvm.org/D17932

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264062 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 16:22:08 +00:00
Daniel Sanders
36aa21137b [mips] Make simm6 consistent with the rest. NFC.
Summary:

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18147


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264057 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 14:50:22 +00:00
Daniel Sanders
7dc891bfa4 [mips] Range check simm7.
Summary:
Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual
encoding (it's a uimm7 except that 0x7f represents -1).

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18145


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264056 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 14:40:00 +00:00
Daniel Sanders
149ab53180 [mips] Range check simm5.
Summary:
We can't check the error message for this one because there's another lw/sw
available that covers a larger range. We therefore check the transition
between the two sizes.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18144


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264054 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 14:29:53 +00:00
Daniel Sanders
c0e5ca9c1c [mips] Range check vsplat_uimm[1234568].
Summary:

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18143


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264053 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 14:17:41 +00:00
Daniel Sanders
e3f4c39d8d [mips] Range check uimm4_ptr, remove uimm6_ptr, and use correctly sized immediates in MSA copy/insert.
Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18142


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264052 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 13:58:53 +00:00
Zinovy Nis
047a636bab [PATCH] Force LoopReroll to reset the loop trip count value after reroll.
It's a bug fix. 
For rerolled loops SE trip count remains unchanged. It leads to incorrect work of the next passes.
My patch just resets SE info for rerolled loop forcing SE to re-evaluate it next time it requested.
I also added a verifier call in the exisitng test to be sure no invalid SE data remain. Without my fix this test would fail with -verify-scev.

Differential Revision: http://reviews.llvm.org/D18316


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264051 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 13:50:57 +00:00
Marina Yatsina
02b7dd6f82 [ELF][gcc compatibility]: support section names with special characters (e.g. "/")
Adding support for section names with special characters in them (e.g. "/").
GCC successfully compiles such section names.
This also fixes PR24520.

Differential Revision: http://reviews.llvm.org/D15678



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264038 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 11:23:15 +00:00
Mehdi Amini
ba3fe48d48 Rename DenseMap::resize() into DenseMap::reserve() (NFC)
This is more coherent with usual containers.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264026 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 07:20:00 +00:00
Junmo Park
f04d589b26 Minor code cleanup. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264024 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 04:37:32 +00:00
Sanjoy Das
1ceb821951 Add "first class" lowering for deopt operand bundles
Summary:
After this change, deopt operand bundles can be lowered directly by
SelectionDAG into STATEPOINT instructions (which are then lowered to a
call or sequence of nop, with an associated __llvm_stackmaps entry0.
This obviates the need to round-trip deoptimization state through
gc.statepoint via RewriteStatepointsForGC.

Reviewers: reames, atrick, majnemer, JosephTremoulet, pgavlin

Subscribers: sanjoy, mcrosier, majnemer, llvm-commits

Differential Revision: http://reviews.llvm.org/D18257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264015 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-22 00:59:13 +00:00
Mike Aizatsky
668a12461d [sancov] do not instrument nodes that are full pre-dominators
Summary:
Without tree pruning clang has 2,667,552 points.
Wiht only dominators pruning: 1,515,586.
With both dominators & predominators pruning: 1,340,534.

Resubmit of r262103.

Differential Revision: http://reviews.llvm.org/D18341

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264003 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 23:08:16 +00:00
Nicolai Haehnle
3f4c92194f AMDGPU: Fix dangling references introduced by r263982
Fixes Valgrind errors on the test cases that were reported as failing
by buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264000 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 22:54:02 +00:00
Simon Pilgrim
752e5f9178 [InstCombine] Ensure all undef operands are handled before binary instruction constant folding
As noted in PR18355, this patch makes it clear that all cases with undef operands have been handled before further constant folding is attempted.

Differential Revision: http://reviews.llvm.org/D18305

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263994 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 22:15:50 +00:00
Duncan P. N. Exon Smith
814be6ba00 Fix -Wdocumentation warnings from r263853
Thanks to chapuni for catching this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263993 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 22:13:44 +00:00
George Burgess IV
127a8ddf85 [MemorySSA] Consider def-only BBs for live-in calculations.
If we have a BB with only MemoryDefs, live-in calculations will ignore
it. This means we get results like this:

define void @foo(i8* %p) {
  ; 1 = MemoryDef(liveOnEntry)
  store i8 0, i8* %p
  br i1 undef, label %if.then, label %if.end

if.then:
  ; 2 = MemoryDef(1)
  store i8 1, i8* %p
  br label %if.end

if.end:
  ; 3 = MemoryDef(1)
  store i8 2, i8* %p
  ret void
}

...When there should be a MemoryPhi in the `if.end` BB.

This patch fixes that behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263991 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 21:25:39 +00:00
Nicolai Haehnle
739e4c8f8b AMDGPU: Coding style fixes
I meant to add these before committing r263982 as per the review,
but I forgot to squash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263983 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:39:24 +00:00
Nicolai Haehnle
f0b7f107b9 AMDGPU: Add SIWholeQuadMode pass
Summary:
Whole quad mode is already enabled for pixel shaders that compute
derivatives, but it must be suspended for instructions that cause a
shader to have side effects (i.e. stores and atomics).

This pass addresses the issue by storing the real (initial) live mask
in a register, masking EXEC before instructions that require exact
execution and (re-)enabling WQM where required.

This pass is run before register coalescing so that we can use
machine SSA for analysis.

The changes in this patch expose a problem with the second machine
scheduling pass: target independent instructions like COPY implicitly
use EXEC when they operate on VGPRs, but this fact is not encoded in
the MIR. This can lead to miscompilation because instructions are
moved past changes to EXEC.

This patch fixes the problem by adding use-implicit operands to
target independent instructions. Some general codegen passes are
relaxed to work with such implicit use operands.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: MatzeB, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18162

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263982 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:28:33 +00:00
Krzysztof Parzyszek
3a1da81cd1 [Hexagon] Add handling fixups and instruction relaxation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263981 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:27:17 +00:00
Krzysztof Parzyszek
1608a747d5 [Hexagon] Properly encode registers in duplex instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263980 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:13:33 +00:00
Krzysztof Parzyszek
2be5a89f8e [Hexagon] Fix reserving emergency spill slots for register scavenger
- R10 and R11 are not reserved registers.
- Check for reserved registers when finding unused caller-saved registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263977 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 19:57:08 +00:00