Commit Graph

145502 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin
0bf4d71d50 Correct register pressure calculation in presence of subregs
If a subreg is used in an instruction it counts as a whole superreg
for the purpose of register pressure calculation. This patch corrects
improper register pressure calculation by examining operand's lane mask.

Differential Revision: https://reviews.llvm.org/D29835

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296009 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 20:19:44 +00:00
Ahmed Bougacha
5487126153 [ORE] Use const CodeRegions in the remark diagnostics. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296008 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 19:17:34 +00:00
Ahmed Bougacha
9628c84c3f [CodeGen] Add a way to SkipDebugLoc in MachineInstr::print(). NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296007 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 19:17:31 +00:00
Ahmed Bougacha
33f4d46446 [GlobalISel] Simplify Select type cleanup using a ScopeExit. NFC.
This lets us use more natural early-returns when selection fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296006 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 19:17:24 +00:00
Adrian Prantl
84277628a6 Revert "Teach the IR verifier to reject conflicting debug info for function arguments."
This reverts commit r295749 while investigating PR32042.

It looks like this check uncovered a problem in the frontend that
needs to be fixed before the check can be enabled again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296005 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 19:13:48 +00:00
Sanjay Patel
b41562fd38 [DAG] add convenience function to get -1 constant; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296004 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 19:02:33 +00:00
Chad Rosier
b81558a8e1 [Reassociate] Add negated value of negative constant to the Duplicates list.
In OptimizeAdd, we scan the operand list to see if there are any common factors
between operands that can be factored out to reduce the number of multiplies
(e.g., 'A*A+A*B*C+D' -> 'A*(A+B*C)+D'). For each operand of the operand list, we
only consider unique factors (which is tracked by the Duplicate set). Now if we
find a factor that is a negative constant, we add the negated value as a factor
as well, because we can percolate the negate out. However, we mistakenly don't
add this negated constant to the Duplicates set.

Consider the expression A*2*-2 + B. Obviously, nothing to factor.

For the added value A*2*-2 we over count 2 as a factor without this change,
which causes the assert reported in PR30256.  The problem is that this code is
assuming that all the multiply operands of the add are already reassociated.
This change avoids the issue by making OptimizeAdd tolerate multiplies which
haven't been completely optimized; this sort of works, but we're doing wasted
work: we'll end up revisiting the add later anyway.

Another possible approach would be to enforce RPO iteration order more strongly.
If we have RedoInsts, we process them immediately in RPO order, rather than
waiting until we've finished processing the whole function. Intuitively, it
seems like the natural approach: reassociation works on expression trees, so
the optimization only works in one direction. That said, I'm not sure how
practical that is given the current Reassociate; the "optimal" form for an
expression depends on its use list (see all the uses of "user_back()"), so
Reassociate is really an iterative optimization of sorts, so any changes here
would probably get messy.

PR30256

Differential Revision: https://reviews.llvm.org/D30228

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296003 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 18:49:03 +00:00
Dehao Chen
aa262b8b29 Use base discriminator in sample pgo profile matching.
Summary: The discriminator has been encoded, and only the base discriminator should be used during profile matching.

Reviewers: dblaikie, davidxl

Reviewed By: dblaikie, davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30218

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295999 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 18:27:45 +00:00
Krzysztof Parzyszek
ab761176c9 [Hexagon] Avoid IMPLICIT_DEFs as new-value producers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295997 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 17:47:34 +00:00
Adam Nemet
e73243639a [LazyMachineBFI] Reimplement with getAnalysisIfAvailable
Since LoopInfo is not available in machine passes as universally as in IR
passes, using the same approach for OptimizationRemarkEmitter as we did for IR
will run LoopInfo and DominatorTree unnecessarily.  (LoopInfo is not used
lazily by ORE.)

To fix this, I am modifying the approach I took in D29836.  LazyMachineBFI now
uses its client passes including MachineBFI itself that are available or
otherwise compute them on the fly.

So for example GreedyRegAlloc, since it's already using MBFI, will reuse that
instance.  On the other hand, AsmPrinter in Justin's patch will generate DT,
LI and finally BFI on the fly.

(I am of course wondering now if the simplicity of this approach is even
preferable in IR.  I will do some experiments.)

Testing is provided by an updated version of D29837 which requires Justin's
patch to bring ORE to the AsmPrinter.

Differential Revision: https://reviews.llvm.org/D30128

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295996 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 17:30:01 +00:00
Filipe Cabecinhas
c5d447ad77 [AddressSanitizer] Add PS4 offset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295994 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 17:10:28 +00:00
Sanjay Patel
243d7e32bc [InstCombine] use loop instead of recursion to peek through FPExt; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295992 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 16:39:51 +00:00
Sanjay Patel
8add37f8a7 [InstCombine] use 'match' to reduce code; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295991 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 16:26:03 +00:00
Jan Vesely
dae323db22 AMDGPU/SI: Fix trunc i16 pattern
Hit on ASICs that support 16bit instructions.

Differential Revision: https://reviews.llvm.org/D30281

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295990 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 16:12:21 +00:00
Simon Pilgrim
65875f1c7e Strip trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295989 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 16:07:04 +00:00
Krzysztof Parzyszek
69d8d82e3c [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295981 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 15:02:09 +00:00
Tobias Grosser
34c1d56ba3 [docs] Add information about how to checkout polly to getting started page
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295974 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 14:27:07 +00:00
Diana Picus
31d09e83a5 [ARM] GlobalISel: Lower call returns
Introduce a common ValueHandler for call returns and formal arguments, and
inherit two different versions for handling the differences (at the moment the
only difference is the way physical registers are marked as used).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295973 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 14:18:41 +00:00
Alexey Bataev
bfa45208ee [SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong
result

Summary:
If the same value is used several times as an extra value, SLP
vectorizer takes it into account only once instead of actual number of
using.
For example:
```
int val = 1;
for (int y = 0; y < 8; y++) {
  for (int x = 0; x < 8; x++) {
    val = val + input[y * 8 + x] + 3;
  }
}
```
We have 2 extra rguments: `1` - initial value of horizontal reduction
and `3`, which is added 8*8 times to the reduction. Before the patch we
added `1` to the reduction value and added once `3`, though it must be
added 64 times.

Reviewers: mkuper, mzolotukhin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295972 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 13:37:09 +00:00
Diana Picus
5e98318841 [ARM] GlobalISel: Lower call parameters in regs
Add support for lowering calls with parameters than can fit into regs.  Use the
same ValueHandler that we used for function returns, but rename it to match its
new, extended purpose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295971 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 13:25:43 +00:00
Ayman Musa
6f30b9797e [X86][AVX] Disable VCVTSS2SD & VCVTSD2SS memory folding and fix the register class of their first input when creating node in fast-isel.
(Quick fix to buildbot failure after rL295940 commit).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295970 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 13:15:44 +00:00
Simon Dardis
fd4603cd6b [mips][ias] Further relax operands of certain assembly instructions
This patch adjusts the most relaxed predicate of immediate operands to accept
immediate forms such as ~(0xf0000000|0x000f00000). Previously these forms
would be accepted by GAS and rejected by IAS.

This partially resolves PR/30383.

Thanks to Sean Bruno for reporting the issue!

Reviewers: slthakur, seanbruno

Differential Revision: https://reviews.llvm.org/D29218



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295965 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 12:40:58 +00:00
Kristof Beyls
93418eeb1d Fix assertion failure in ARMConstantIslandPass.
The ARMConstantIslandPass didn't have support for handling accesses to
constant island objects through ARM::t2LDRBpci instructions. This adds
support for that.

This fixes PR31997.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295964 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 12:24:55 +00:00
Simon Pilgrim
ee4b4ec8cc Fix signed/unsigned comparison warning on MSVC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295962 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 12:00:34 +00:00
Alexey Bataev
8188e22176 Revert "[SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong"
This reverts commit 7c5141e577d9efd1c8e3087566a38ce6b3a41a84.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295957 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 11:09:35 +00:00
Alexey Bataev
4ef753a118 [SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong
result

Summary:
If the same value is used several times as an extra value, SLP
vectorizer takes it into account only once instead of actual number of
using.
For example:
```
int val = 1;
for (int y = 0; y < 8; y++) {
  for (int x = 0; x < 8; x++) {
    val = val + input[y * 8 + x] + 3;
  }
}
```
We have 2 extra rguments: `1` - initial value of horizontal reduction
and `3`, which is added 8*8 times to the reduction. Before the patch we
added `1` to the reduction value and added once `3`, though it must be
added 64 times.

Reviewers: mkuper, mzolotukhin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295956 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 10:57:15 +00:00
Alexey Bataev
8d04a8701d Revert "[SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong"
This reverts commit d83c81ee6a8dea662808ac22b396d1bb0595c89d.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295951 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 09:59:29 +00:00
Alexey Bataev
29965753c8 [SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong
result

Summary:
If the same value is used several times as an extra value, SLP
vectorizer takes it into account only once instead of actual number of
using.
For example:
```
int val = 1;
for (int y = 0; y < 8; y++) {
  for (int x = 0; x < 8; x++) {
    val = val + input[y * 8 + x] + 3;
  }
}
```
We have 2 extra rguments: `1` - initial value of horizontal reduction
and `3`, which is added 8*8 times to the reduction. Before the patch we
added `1` to the reduction value and added once `3`, though it must be
added 64 times.

Reviewers: mkuper, mzolotukhin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295949 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 09:40:38 +00:00
Ayman Musa
ff35eecd7d [X86][AVX512] Remove VCVTSS2SDZ & VCVTSD2SSZ from memory folding tables as they introduce new read dependency when folding.
(Quick fix to buildbot fail). 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295946 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 08:13:36 +00:00
Ayman Musa
70ad23eba8 [X86][AVX512] Change VCVTSS2SD and VCVTSD2SS node types to keep consistency between VEX/EVEX versions.
AVX versions of the converts work on f32/f64 types, while AVX512 version work on vectors.

Differential Revision: https://reviews.llvm.org/D29988



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295940 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 07:24:21 +00:00
Matt Arsenault
210095c5c9 LoadStoreVectorizer: Split even sized illegal chains properly
Implement isLegalToVectorizeLoadChain for AMDGPU to avoid
producing private address spaces accesses that will need to be
split up later. This was doing the wrong thing in the case
where the queried chain was an even number of elements.

A possible <4 x i32> store was being split into
store <2 x i32>
store i32
store i32

rather than
store <2 x i32>
store <2 x i32>

when legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295933 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 03:58:53 +00:00
Craig Topper
59900325da [X86][IR] In AutoUpgrade, check explicitly for xop.vpcmov and xop.vpcmov.256 instead of anything starting with xop.vpcmov
There were some older intrinsics that only existed for less than a month in 2012 that still exist in some out of tree test files that start with this string, but aren't able to be handled by the current upgrade code and fire an assert. Now we'll go back to treating them as not intrinsics at all and just passing them through to output.

Fixes PR32041, sort of.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295930 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 03:22:14 +00:00
Matt Arsenault
5736385164 TargetOptions: Fix not accounting for NoSignedZerosFPMath in ==
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295928 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 03:16:44 +00:00
Matthias Braun
090bead49c Test if we can use raw strings on all platforms compiling LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295917 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 01:09:01 +00:00
Eli Friedman
e597c2c861 Explicitly state the behavior of inbounds with a null pointer.
See https://llvm.org/bugs/show_bug.cgi?id=31439; this reflects LLVM's
behavior in practice, and should be compatible with C/C++ rules.

Differential Revision: https://reviews.llvm.org/D28026



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295916 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 00:48:18 +00:00
Matt Arsenault
5925762682 AMDGPU: Replace disabled exp inputs with undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295914 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 00:44:03 +00:00
Matt Arsenault
32a81bbff2 AMDGPU: Add another BFE pattern
This is the pattern that falls out of the instruction's
definition if offset == 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295912 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-23 00:23:43 +00:00
Matt Arsenault
cd39b42cab AMDGPU: Use clamp with f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295908 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 23:53:37 +00:00
Michael Kuperstein
c6527c8786 Revert r295868 because it breaks a different SLP lit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295906 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 23:35:13 +00:00
Matt Arsenault
e184e01dd7 AMDGPU: Fold FP clamp as modifier bit
The manual is unclear on the details of this. It's not
clear to me if denormals are not allowed with clamp,
or if that is only omod. Not allowing denorms for
fp16 or fp64 isn't useful so I also question if that
is really a restriction. Same with whether this is valid
without IEEE mode enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295905 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 23:27:53 +00:00
Wei Ding
1cfed01e02 AMDGPU : Update TrapCode based on Trap Handler ABI.
Differential Revision: http://reviews.llvm.org/D30232

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295904 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 23:22:19 +00:00
Justin Bogner
af8c7cedc1 [libFuzzer] Update traces hooks test after r293741
This test now passes on darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295902 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 23:12:36 +00:00
Justin Bogner
28c53fa4a0 [libFuzzer] Mark a test that infinite loops as unsupported
We need to investigate this, but for now it just causes too much
headache when trying to run these tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295900 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 23:05:17 +00:00
Matt Arsenault
c2d34b5027 AMDGPU: Add replacement bfe intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295899 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 23:04:58 +00:00
Sanjay Patel
9ba3c4dd5a [InstCombine] don't try SimplifyDemandedInstructionBits from add/sub because it's slow and unlikely to succeed
Notably, no regression tests change when we remove these calls, and these are expensive calls.

The motivation comes from the general acknowledgement that the compiler is getting slower:
http://lists.llvm.org/pipermail/llvm-dev/2017-January/109188.html
http://lists.llvm.org/pipermail/llvm-dev/2016-December/108279.html

And specifically the test case attached to PR32037:
https://bugs.llvm.org//show_bug.cgi?id=32037

Profiling the middle-end (opt) part of the compile:
$ ./opt -O2 row_common.bc -o /dev/null

...visitAdd and visitSub are near the top of the instcombine list, and the calls to SimplifyDemandedInstructionBits()
are high within each of those. Those calls account for 1%+ of the opt time in either debug or release profiles. And 
that's the rough win I see from this patch when testing opt built release from r295864 on an iMac with Haswell 4GHz
(model 4790K).

It seems unlikely that we'd be able to eliminate add/sub or change their operands given that add/sub normally affect
all bits, and the PR32037 example shows no IR difference after this change using -O2.

Also worth noting - the code comment in visitAdd:
// This handles stuff like (X & 254)+1 -> (X&254)|1
...isn't true. That transform is handled later with a call to haveNoCommonBitsSet().

Differential Revision: https://reviews.llvm.org/D30270


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295898 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 23:01:12 +00:00
Dylan McKay
ec26388916 [AVR] Disable integrated assembler for a few tests
Fixes the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295895 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 22:41:13 +00:00
Eugene Zelenko
096e40d35f [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295893 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 22:32:51 +00:00
Krzysztof Parzyszek
e9d7ca1b92 [Hexagon] Implement @llvm.readcyclecounter()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295892 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 22:28:47 +00:00
Matt Arsenault
206dfa3c0d AMDGPU: Don't add emergency stack slot if all spills are SGPR->VGPR
This should avoid reporting any stack needs to be allocated in the
case where no stack is truly used. An unused stack slot is still
left around in other cases where there are real stack objects
but no spilling occurs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295891 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 22:23:32 +00:00
Daniel Berlin
4ddfe6915d PredicateInfo: Support switch statements
Summary:
Depends on D29606 and D29682

Makes us pass GVN's edge.ll (we also will pass a few other testcases
they just need cleaning up).

Thoughts on the Predicate* hiearchy of classes especially welcome :)
(it's not clear to me how best to organize it, and currently, the getBlock* seems ... uglier than maybe wasting a field somewhere or something).

Reviewers: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29747

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295889 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-22 22:20:58 +00:00