Commit Graph

129871 Commits

Author SHA1 Message Date
Chad Rosier
b0bab88f96 Simplify logic. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265537 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 13:27:13 +00:00
Silviu Baranga
39fbde60e1 [SCEV] Introduce a guarded backedge taken count and use it in LAA and LV
Summary:
When the backedge taken codition is computed from an icmp, SCEV can
deduce the backedge taken count only if one of the sides of the icmp
is an AddRecExpr. However, due to sign/zero extensions, we sometimes
end up with something that is not an AddRecExpr.

However, we can use SCEV predicates to produce a 'guarded' expression.
This change adds a method to SCEV to get this expression, and the
SCEV predicate associated with it.

In HowManyGreaterThans and HowManyLessThans we will now add a SCEV
predicate associated with the guarded backedge taken count when the
analyzed SCEV expression is not an AddRecExpr. Note that we only do
this as an alternative to returning a 'CouldNotCompute'.

We use new feature in Loop Access Analysis and LoopVectorize to analyze
and transform more loops.

Reviewers: anemet, mzolotukhin, hfinkel, sanjoy

Subscribers: flyingforyou, mcrosier, atrick, mssimpso, sanjoy, mzolotukhin, llvm-commits

Differential Revision: http://reviews.llvm.org/D17201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265535 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 13:18:26 +00:00
Evgeny Astigeevich
864fed9d22 [AArch64][CodeGen] NFC refactor AArch64InstrInfo::optimizeCompareInstr to prepare it for fixing a bug in it
AArch64InstrInfo::optimizeCompareInstr has a bug which causes generation of incorrect code (PR#27158).
The patch refactors the function to simplify reviewing the fix of the bug.

1. Function name ‘modifiesConditionCode’ is changed to ‘areCFlagsAccessedBetweenInstrs’
   to reflect that the function can check modifying accesses, reading accesses or both.
2. Function ‘AArch64InstrInfo::optimizeCompareInstr’
   - Documented the function
   - Cmp_NZCV is DeadNZCVIdx to reflect that it is an operand index of dead NZCV
   - The code for the case of substituting CmpInstr is put into separate
     functions the main of them is ‘substituteCmpInstr’.

Differential Revision: http://reviews.llvm.org/D18609



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265531 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 11:39:00 +00:00
Chuang-Yu Cheng
6b74529a35 [ppc64] Temporary disable sibling call optimization on ppc64 due to breaking test case
r265506 breaks print-stack-trace.cc test case of compiler-rt in bootstrap
test.

http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/1708

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265528 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 10:48:36 +00:00
David Majnemer
8b680c27be [SLPVectorizer] Vectorizing the libm sqrt to llvm's sqrt intrinsic requires nnan
To quote the langref "Unlike sqrt in libm, however, llvm.sqrt has
undefined behavior for negative numbers other than -0.0 (which allows
for better optimization, because there is no need to worry about errno
being set). llvm.sqrt(-0.0) is defined to return -0.0 like IEEE sqrt."

This means that it's unsafe to replace sqrt with llvm.sqrt unless the
call is annotated with nnan.

Thanks to Hal Finkel for pointing this out!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265521 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 07:04:53 +00:00
Duncan P. N. Exon Smith
adb72b91cb IR: Move MDStrings to a BumpPtrAllocator
We never delete any MDString until the context is destroyed.  Might as
well throw them onto a BumpPtrAllocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265520 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 06:41:54 +00:00
Duncan P. N. Exon Smith
e49dfa7e9a IRMover: Steal arguments when moving functions, NFC
Instead of copying arguments from the source function to the
destination, steal them.  This has a few advantages.

  - The ValueMap doesn't need to be seeded with (or cleared of)
    Arguments.

  - Often the destination function won't have created any arguments yet,
    so this avoids malloc traffic.

  - Argument names don't need to be copied.

Because argument lists are lazy, this required a new
Function::stealArgumentListFrom helper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265519 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 06:38:15 +00:00
Davide Italiano
f504f6f4f7 Revert "[IRVerifier] Don't crash on invalid DIFile inside DISubprogram."
This reverts commit r265515 as lots of tests need to be fixed before
this actually can go in.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265517 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 04:34:38 +00:00
Richard Trieu
100a00cda0 Add parentheses to silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265516 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 04:22:00 +00:00
Davide Italiano
ce42332d64 [IRVerifier] Don't crash on invalid DIFile inside DISubprogram.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265515 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 03:57:47 +00:00
Davide Italiano
d7975248c1 [IRVerifier] Avoid crashing on an invalid compile unit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265514 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 03:07:58 +00:00
Matthias Braun
525c4ba52f AArch64: Fix compile error
Fixed to adapt a use of enterBasicBlock() in my last commit (because I
had follow on patches in my repository that change the code).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 02:59:44 +00:00
Matthias Braun
dc2f859a3f RegisterScavenger: Take a reference as enterBasicBlock() argument.
Make it obvious that the argument cannot be nullptr.
Remove an unnecessary nullptr check in initRegState.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265511 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 02:47:09 +00:00
Matthias Braun
72b4fa0d1c LivePhysRegs: removeReg() must remove aliased registers
We must remove all aliased registers which may be more than the all sub
and super registers combined.

Bug found while reading the code. The bug does not affect any existing
target as the only use of register aliases I could found were control
registers on ARM and Hexagon which are all reserved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265510 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 02:46:35 +00:00
Matthias Braun
1685c6f7ca LivePhysRegs: Remove redundant check
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265509 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 02:46:04 +00:00
Duncan P. N. Exon Smith
15709846d4 ValueMapper: Fix delayed blockaddress handling after r265273
r265273 added Mapper::mapBlockAddress, which delays mapping a
blockaddress value until the function has a body.  The condition was
backwards, and should be checking Function::empty instead of
GlobalValue::isDeclaration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265508 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 02:25:12 +00:00
Duncan P. N. Exon Smith
13d5c58951 AsmParser: Don't crash on unresolved !tbaa
Instead of crashing, give a nice error.  As a drive-by, fix the location
associated with the errors for unresolved metadata (the location was off
by one token).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265507 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 02:06:40 +00:00
Chuang-Yu Cheng
4f461cab38 [ppc64] Enable sibling call optimization on ppc64 ELFv1/ELFv2 abi
This patch enable sibling call optimization on ppc64 ELFv1/ELFv2 abi, and
add a couple of test cases. This patch also passed llvm/clang bootstrap
test, and spec2006 build/run/result validation.

Original issue: https://llvm.org/bugs/show_bug.cgi?id=25617

Great thanks to Tom's (tjablin) help, he contributed a lot to this patch.
Thanks Hal and Kit's invaluable opinions!

Reviewers: hfinkel kbarton

http://reviews.llvm.org/D16315

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265506 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 02:04:38 +00:00
Chuang-Yu Cheng
ff2190e04a [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance
This patch implement the following instructions:
- addpcis subpcis
- maddhd maddhdu maddld
- modsw moduw modsd modud
- darn
- extswsli extswsli.
- setb
- dtstsfi dtstsfiq

Total 15 instructions

Reviewers: nemanjai hfinkel tjablin amehsan kbarton

http://reviews.llvm.org/D17885

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265505 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 01:47:02 +00:00
Chuang-Yu Cheng
c77546e444 [Power9] Implement copy-paste, msgsync, slb, and stop instructions
This patch implements the following BookII and Book III instructions:
- copy copy_first cp_abort paste paste. paste_last
- msgsync
- slbieg slbsync
- stop

Total 10 instructions

Reviewers: nemanjai hfinkel tjablin amehsan kbarton

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265504 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 01:46:45 +00:00
Sanjoy Das
376f5bad7b [RS4GC] Add a comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265503 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 01:33:54 +00:00
Sanjoy Das
6dd7334ee8 Lower @llvm.experimental.deoptimize as a noreturn call
While preserving the return value for @llvm.experimental.deoptimize at
the IR level is useful during mid-level optimization, doing so at the
machine instruction level requires generating some extra code and a
return that is non-ideal.  This change has LLVM lower

```
  %val = call @llvm.experimental.deoptimize
  ret %val
```

to effectively

```
  call @__llvm_deoptimize()
  unreachable
```

instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265502 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 01:33:49 +00:00
Tom Stellard
43f537f492 AMDGPU: Document address space mapping
Summary:
Address space mapping is described in lib/Target/AMDGPU/AMDGPU.h in
Doxygen comments. This patch adds the description to user guide for
AMDGPU back-end.

Patch By: Vedran Miletić

Reviewers: tstellarAMD, arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17046

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265500 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 01:29:19 +00:00
NAKAMURA Takumi
43e8875502 AArch64CodeGen: Make AArch64RegisterBankInfo.cpp optional along LLVM_BUILD_GLOBAL_ISEL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265499 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 01:18:08 +00:00
David Majnemer
731666ee90 [SLPVectorizer] Vectorize libcalls of sqrt
We didn't realize that we could transform the libcall into a vectorized
intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265493 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-06 00:14:59 +00:00
Quentin Colombet
c37faf21d0 [RegisterBankInfo] Include RegisterBank.h.
We actually need the definition of a RegisterBank to be able to inline
the implementation of the subscript operator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265492 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:57:25 +00:00
Quentin Colombet
717601810e [RegisterBankInfo] Add missing include for assert.
This should appease the linux bot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265491 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:43:58 +00:00
Davide Italiano
fe735e5923 [DebugInfo] Fix tests so that each subprogram belongs to a CU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265490 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:37:08 +00:00
Quentin Colombet
9c7eb243ef [AArch64] Initial implementation of the targeting of the register bank information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265489 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:34:59 +00:00
Quentin Colombet
6443af0d08 [RegisterBankInfo] Simplify the API for build a register bank.
As part of the TRI argument of addRegBankCoverage we already have access to
the TargetRegisterClass through the ID of that register class.
Therefore, there is no point in needing a TargetRegisterClass instance,
the ID is enough to get to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265487 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:26:39 +00:00
Sanjoy Das
8e366b3614 [RS4GC] NFC cleanup of the DeferredReplacement class
Instead of constructors use clearly named factory methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265486 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:18:53 +00:00
Sanjoy Das
0ed4be724f [RS4GC] Better codegen for deoptimize calls
Don't emit a gc.result for a statepoint lowered from
@llvm.experimental.deoptimize since the call into __llvm_deoptimize is
effectively noreturn.  Instead follow the corresponding gc.statepoint
with an "unreachable".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265485 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:18:35 +00:00
Quentin Colombet
5a3e3ec846 [Target] Remove a deprecated comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265484 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 23:04:54 +00:00
Quentin Colombet
ca7369ade3 [Target] Add an accessor to the register bank information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265483 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 22:50:40 +00:00
Manman Ren
cf18232c49 Swift Calling Convention: swiftcc for ARM.
Differential Revision: http://reviews.llvm.org/D18769


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265482 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 22:44:44 +00:00
Evgeniy Stepanov
9c4431f3cb Faster stack-protector for Android/AArch64.
Bionic has a defined thread-local location for the stack protector
cookie. Emit a direct load instead of going through __stack_chk_guard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265481 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 22:41:50 +00:00
Manman Ren
1f7638e1cb Swift Calling Convention: add swiftcc.
Differential Revision: http://reviews.llvm.org/D17863


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265480 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 22:41:47 +00:00
Quentin Colombet
2b1f04632c [RegisterBank] Implement the verify method to check for the obvious mistakes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265479 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 22:34:01 +00:00
Quentin Colombet
1f2bf92c75 [RegisterBankInfo] Add debug print to check how the initialization is going.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265475 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:47:56 +00:00
George Burgess IV
a8ddf55110 [CFLAA] Fix PR27213; incorrect tagging of args/globals
Prior to this patch, CFLAA wouldn't tag arguments/globals properly if
it didn't find any "interesting" edges on them. This means that, if all
you do is store constants to a global or argument, we would never
actually treat it as a global/argument.

Test case:

define void @foo(i32* %A, i32* %B) #0 {
entry:
  store i32 0, i32* %A, align 4
  store i32 0, i32* %B, align 4
  ret void
}

CFLAA would say that %A can't alias %B, because neither pointer was
used in an interesting way. This patch makes us note whether something
is an argument, global, ... regardless of how interesting CFLAA thinks
its uses are.

(For the record, using a value in an interesting way means loading
from it, using it in a GEP, ...)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265474 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:40:45 +00:00
Quentin Colombet
6077d14b60 [RegisterBank] Add printable capabilities for future debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265473 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:40:43 +00:00
Duncan P. N. Exon Smith
ea1a7b0666 Try harder to appease MSVC after r265456
r265465 wasn't good enough.  I need to spell out all the moves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265470 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:25:33 +00:00
Quentin Colombet
ccd741b08a [RegisterBankInfo] Make addRegBankCoverage more capable to ease
targeting jobs.
Now, addRegBankCoverage also adds the subreg-classes not just the
sub-classes of the given register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265469 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:20:12 +00:00
Junmo Park
748423059f Minor code cleanups. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265468 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:14:31 +00:00
Duncan P. N. Exon Smith
d7773c0d39 IR: Introduce ConstantAggregate, NFC
Add a common parent class for ConstantArray, ConstantVector, and
ConstantStruct called ConstantAggregate.  These are the aggregate
subclasses of Constant that take operands.

This is mainly a cleanup, adding common `isa` target and removing
duplicated code.  However, it also simplifies caching which constants
point transitively at `GlobalValue` (a possible future direction).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265466 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:10:45 +00:00
Duncan P. N. Exon Smith
3444a406d3 Try to appease MSVC after r265456
I can't remember if adding `= default` will make MSVC happy, or if I
have to spell this out.  Let's try the cleaner version first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265465 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:07:01 +00:00
Quentin Colombet
062bf7c9dd [RegisterBankInfo] Implement the methods to create register banks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265464 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 21:06:15 +00:00
Duncan P. N. Exon Smith
ef94029809 IR: Add missing assertion for ConstantVector::ConstantVector
Use the same assertion as ConstantArray.  Vectors should have the right
number of elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265463 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 20:53:47 +00:00
Quentin Colombet
aa40fb64ae [RegisterBank] Provide a way to check if a register bank is valid.
Change the default constructor to create invalid object.
The target will have to properly initialize the register banks before
using them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265460 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 20:48:32 +00:00
Duncan P. N. Exon Smith
2707ee3256 Revert "Fix Clang-tidy modernize-deprecated-headers warnings in remaining files; other minor fixes."
This reverts commit r265454 since it broke the build.  E.g.:

  http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_build/22413/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265459 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-05 20:45:04 +00:00