1129 Commits

Author SHA1 Message Date
Craig Topper
85f08cc0b8 [Hexagon] Set ctlz_zero_undef/cttz_zero_undef to Expand so LegalizeDAG will convert them to ctlz/cttz. Remove the now unneccessary isel patterns. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267266 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-23 02:49:31 +00:00
Krzysztof Parzyszek
37cfc23682 [Hexagon] Use common Pat classes for selecting code for intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267178 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 18:05:55 +00:00
Krzysztof Parzyszek
d12b34532a [Hexagon] Properly close live range in HexagonBlockRanges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267173 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 17:27:22 +00:00
Krzysztof Parzyszek
db55335b2e [Hexagon] Teach mux expansion how to deal with undef predicates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267165 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 16:47:01 +00:00
Krzysztof Parzyszek
58d0f74c14 [Hexagon] Add definitions for trap/pause instructions
Also add tests for other instructions from HexagonSystemInst.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267162 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 16:25:00 +00:00
Krzysztof Parzyszek
ad7d56b336 [Hexagon] Properly recognize register alt names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267038 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 19:49:53 +00:00
Krzysztof Parzyszek
c552ed7f63 [Hexagon] Expand handling of the small-data/bss section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267034 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 18:56:45 +00:00
Krzysztof Parzyszek
de21c29b93 [Hexagon] Add -mv.. options to override CPU selection
This is for compatibility with scripts that use -mv5, etc. with the
assembler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266918 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-20 21:17:40 +00:00
Krzysztof Parzyszek
4a0bd4e1e3 [Hexagon] Fix handling of lcomm directive
Patch by Colin LeMahieu.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266882 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-20 15:54:13 +00:00
Krzysztof Parzyszek
dc458b494e [RDF] Consider register as live if any alias is live
This only affects the recomputation of kill flags.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266875 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-20 14:33:23 +00:00
Krzysztof Parzyszek
414bb96c93 [Hexagon] Fix operand swapping in HexagonPeephole
Also, disable zero- and size-extend optimizations for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266821 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-19 21:36:24 +00:00
Krzysztof Parzyszek
2d715342de [Hexagon] Fix printing the address operand of S2_storerinewabs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266811 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-19 20:20:33 +00:00
Krzysztof Parzyszek
1c960f5468 [Hexagon] Implement branch relaxation
Patch by Sirish Pande.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266792 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-19 18:30:18 +00:00
Mehdi Amini
f6071e14c5 [NFC] Header cleanup
Removed some unused headers, replaced some headers with forward class declarations.

Found using simple scripts like this one:
clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap'

Patch by Eugene Kosov <claprix@yandex.ru>

Differential Revision: http://reviews.llvm.org/D19219

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266595 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-18 09:17:29 +00:00
Craig Topper
cc9f5cb25c Use MVT instead of EVT to remove a bunch of unnecessary calls to getSimpleVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266414 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-15 06:20:21 +00:00
Derek Schuff
9b3da26fa8 Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
Summary:
This adds the same checks that were added in r264593 to all
target-specific passes that run after register allocation.

Reviewers: qcolombet

Subscribers: jyknight, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18525

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265313 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-04 17:09:25 +00:00
Hans Wennborg
f864a32c13 Change eliminateCallFramePseudoInstr() to return an iterator
This will become necessary in a subsequent change to make this method
merge adjacent stack adjustments, i.e. it might erase the previous
and/or next instruction.

It also greatly simplifies the calls to this function from Prolog-
EpilogInserter. Previously, that had a bunch of logic to resume iteration
after the call; now it just continues with the returned iterator.

Note that this changes the behaviour of PEI a little. Previously,
it attempted to re-visit the new instruction created by
eliminateCallFramePseudoInstr(). That code was added in r36625,
but I can't see any reason for it: the new instructions will obviously
not be pseudo instructions, they will not have FrameIndex operands,
and we have already accounted for the stack adjustment.

Differential Revision: http://reviews.llvm.org/D18627

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265036 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-31 18:33:38 +00:00
Krzysztof Parzyszek
3fb5c4321a [Hexagon] Improve handling of unaligned vector loads and stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264584 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-28 15:43:03 +00:00
Krzysztof Parzyszek
621888ea62 [Hexagon] Only use restore functions for single register at -Oz
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264581 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-28 14:52:21 +00:00
Krzysztof Parzyszek
678eebccaf [Hexagon] Speed up frame lowering when no optimizations are enabled
- Do not optimize stack slots in optnone functions.
- Get aligned-base register from HexagonMachineFunctionInfo instead of
  looking for ALIGNA instruction in the function's body.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264580 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-28 14:42:03 +00:00
Krzysztof Parzyszek
d593c6f133 [Hexagon] Be sure to treat subregisters of a CSR as CSRs as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264331 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 20:31:41 +00:00
Krzysztof Parzyszek
d4af74e531 [Hexagon] Add support for run-time stack overflow checking
Patch by Sundeep Kushwaha.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264328 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 20:20:07 +00:00
Krzysztof Parzyszek
deffc78c77 [Hexagon] Generate PIC-specific versions of save/restore routines
In PIC mode, the registers R14, R15 and R28 are reserved for use by
the PLT handling code. This causes all functions to clobber these
registers. While this is not new for regular function calls, it does
also apply to save/restore functions, which do not follow the standard
ABI conventions with respect to the volatile/non-volatile registers.

Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264324 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 19:18:48 +00:00
Krzysztof Parzyszek
3a1da81cd1 [Hexagon] Add handling fixups and instruction relaxation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263981 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:27:17 +00:00
Krzysztof Parzyszek
1608a747d5 [Hexagon] Properly encode registers in duplex instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263980 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 20:13:33 +00:00
Krzysztof Parzyszek
2be5a89f8e [Hexagon] Fix reserving emergency spill slots for register scavenger
- R10 and R11 are not reserved registers.
- Check for reserved registers when finding unused caller-saved registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263977 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-21 19:57:08 +00:00
James Y Knight
ceb61bf42f Tweak some atomics functions in preparation for larger changes; NFC.
- Rename getATOMIC to getSYNC, as llvm will soon be able to emit both
  '__sync' libcalls and '__atomic' libcalls, and this function is for
  the '__sync' ones.

- getInsertFencesForAtomic() has been replaced with
  shouldInsertFencesForAtomic(Instruction), so that the decision can be
  made per-instruction. This functionality will be used soon.

- emitLeadingFence/emitTrailingFence are no longer called if
  shouldInsertFencesForAtomic returns false, and thus don't need to
  check the condition themselves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263665 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-16 22:12:04 +00:00
Colin LeMahieu
f0ac61f720 [Hexagon] Adding missing break in switch statement. Extra operands would have been appended to the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263657 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-16 20:00:38 +00:00
Sanjay Patel
9d31cd8fef [DAG] use !isUndef() ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263453 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-14 18:09:43 +00:00
Sanjay Patel
3e87fcf215 [DAG] use isUndef() ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263448 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-14 17:28:46 +00:00
Krzysztof Parzyszek
b6306a8594 [Hexagon] Fix lowering of calls with the return type of i1
This fixes an assertion in test/CodeGen/Hexagon/ifcvt-edge-weight.ll
when run with -debug-only=isel



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262726 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-04 17:38:05 +00:00
Colin LeMahieu
71381aee13 [NFC] Convert tabs to spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262411 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-01 22:05:03 +00:00
Colin LeMahieu
9371f402bc [Hexagon] Modifying r262258 to only be in effect in the hand assembler path, not the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262400 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-01 21:37:41 +00:00
Matthias Braun
eab2869a64 TableGen: Check scheduling models for completeness
TableGen checks at compiletime that for scheduling models with
"CompleteModel = 1" one of the following holds:

- Is marked with the hasNoSchedulingInfo flag
- The instruction is a subclass of Sched
- There are InstRW definitions in the scheduling model

Typical steps necessary to complete a model:

- Ensure all pseudo instructions that are expanded before machine
  scheduling (usually everything handled with EmitYYY() functions in
  XXXTargetLowering).
- If a CPU does not support some instructions mark the corresponding
  resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }".
- Add missing scheduling information.

Differential Revision: http://reviews.llvm.org/D17747

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262384 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-01 20:03:21 +00:00
Colin LeMahieu
6e4a4d849c [Hexagon] As a size optimization, not lazy extending TPREL or DTPREL variants since they're usually in range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262258 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-29 21:21:56 +00:00
Colin LeMahieu
adaa70afa6 [Hexagon] Missed member initialization causing ubsan failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262252 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-29 20:42:25 +00:00
Colin LeMahieu
4a487ecba9 [Hexagon] Setting sign mismatch flag on expression instead of using bit tricks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262243 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-29 19:17:56 +00:00
Colin LeMahieu
45a6a62865 [Hexagon] Using MustExtend flag on expression instead of passing around bools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262238 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-29 18:39:51 +00:00
Duncan P. N. Exon Smith
1d75c8d9ec CodeGen: Change MachineInstr to use MachineInstr&, NFC
Change MachineInstr API to prefer MachineInstr& over MachineInstr*
whenever the parameter is expected to be non-null.  Slowly inching
toward being able to fix PR26753.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262149 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-27 20:01:33 +00:00
Duncan P. N. Exon Smith
0ce039da16 CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC
In all but one case, change the DFAPacketizer API to take MachineInstr&
instead of MachineInstr*.  In DFAPacketizer::endPacket(), take
MachineBasicBlock::iterator.  Besides cleaning up the API, this is in
search of PR26753.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262142 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-27 19:09:00 +00:00
Duncan P. N. Exon Smith
63ec7f0445 WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC
Update APIs in MachineInstrBundle.h to take and return MachineInstr&
instead of MachineInstr* when the instruction cannot be null.  Besides
being a nice cleanup, this is tacking toward a fix for PR26753.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262141 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-27 17:05:33 +00:00
Duncan P. N. Exon Smith
42e18357c5 CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC
Take MachineInstr by reference instead of by pointer in SlotIndexes and
the SlotIndex wrappers in LiveIntervals.  The MachineInstrs here are
never null, so this cleans up the API a bit.  It also incidentally
removes a few implicit conversions from MachineInstrBundleIterator to
MachineInstr* (see PR26753).

At a couple of call sites it was convenient to convert to a range-based
for loop over MachineBasicBlock::instr_begin/instr_end, so I added
MachineBasicBlock::instrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262115 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-27 06:40:41 +00:00
Hongbin Zheng
5d7472e863 Introduce analysis pass to compute PostDominators in the new pass manager. NFC
Differential Revision: http://reviews.llvm.org/D17537

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261902 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-25 17:54:07 +00:00
Duncan P. N. Exon Smith
5b9b80ea30 CodeGen: TII: Take MachineInstr& in predicate API, NFC
Change TargetInstrInfo API to take `MachineInstr&` instead of
`MachineInstr*` in the functions related to predicated instructions
(I'll try to come back later and get some of the rest).  All of these
functions require non-null parameters already, so references are more
clear.  As a bonus, this happens to factor away a host of implicit
iterator => pointer conversions.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261605 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-23 02:46:52 +00:00
Duncan P. N. Exon Smith
110284e56c CodeGen: Bring back MachineBasicBlock::iterator::getInstrIterator()...
This is a little embarrassing.

When I reverted r261504 (getIterator() => getInstrIterator()) in
r261567, I did a `git grep` to see if there were new calls to
`getInstrIterator()` that I needed to migrate.  There were 10-20 hits,
and I blindly did a `sed ...` before calling `ninja check`.

However, these were `MachineInstrBundleIterator::getInstrIterator()`,
which predated r261567.  Perhaps coincidentally, these had an identical
name and return type.

This commit undoes my careless sed and restores
`MachineBasicBlock::iterator::getInstrIterator()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261577 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-22 21:30:15 +00:00
Duncan P. N. Exon Smith
20a62528ef Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"
This reverts commit r261504, since it's not obvious the new name is
better:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160222/334298.html

I'll recommit if we get consensus that it's the right direction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261567 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-22 20:49:58 +00:00
Duncan P. N. Exon Smith
6e5736e1aa CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC
Delete MachineInstr::getIterator(), since the term "iterator" is
overloaded when talking about MachineInstr.

- Downcast to ilist_node in iplist::getNextNode() and getPrevNode() so
  that ilist_node::getIterator() is still available.
- Add it back as MachineInstr::getInstrIterator().  This matches the
  naming in MachineBasicBlock.
- Add MachineInstr::getBundleIterator().  This is explicitly called
  "bundle" (not matching MachineBasicBlock) to disintinguish it clearly
  from ilist_node::getIterator().
- Update all calls.  Some of these I switched to `auto` to remove
  boiler-plate, since the new name is clear about the type.

There was one call I updated that looked fishy, but it wasn't clear what
the right answer was.  This was in X86FrameLowering::inlineStackProbe(),
added in r252578 in lib/Target/X86/X86FrameLowering.cpp.  I opted to
leave the behaviour unchanged, but I'll reply to the original commit on
the list in a moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261504 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-21 22:58:35 +00:00
Chad Rosier
793d95a1f0 [Hexagon] Remove redundant check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261232 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-18 17:49:57 +00:00
Krzysztof Parzyszek
5270eb997f [Hexagon] Fix compilation error with GCC 6
Compiling Hexagon target with GCC 6 produces "error: should have been
declared inside" due to GCC PR c++/69657 which was merged.

Properly wrapping operator<<() definitions within the namespace llvm
fixes the issue.

Author: domagoj.stolfa

Differential Revision: http://reviews.llvm.org/D17281


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261220 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-18 16:10:27 +00:00
Krzysztof Parzyszek
bfe4c5ff7e [Hexagon] Implement TLS support
Patch by Anand Kodnani.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261218 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-18 15:42:57 +00:00