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15 Commits

Author SHA1 Message Date
Matt Arsenault
0c52bece01 AMDGPU: Fix unnecessary ands when packing f16 vectors 
computeKnownBits didn't handle fp_to_fp16 to report
the high bits as 0. ARM maps the generic node to an instruction
that does not modify the high bits of the register, so introduce
a target node where the high bits are known 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297873 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-15 19:04:26 +00:00
Matt Arsenault
32a81bbff2 AMDGPU: Add another BFE pattern 
This is the pattern that falls out of the instruction's
definition if offset == 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295912 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-23 00:23:43 +00:00
Jan Vesely
6d821c2f7c ADMGPU/EG,CM: Implement _noret global atomics 
_RTN versions will be a lot more complicated

Differential Revision: https://reviews.llvm.org/D28067

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292162 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-16 21:20:13 +00:00
Jan Vesely
53dcfdf89b AMDGPU/EG,CM: Add fp16 conversion instructions 
Differential Revision: https://reviews.llvm.org/D28164

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291622 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-01-11 00:12:39 +00:00
Matt Arsenault
95ec13b22a AMDGPU: Select mulhi 24-bit instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279902 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-08-27 01:32:27 +00:00
Jan Vesely
fc94e66b10 AMDGPU/R600: Convert buffer id to VTX_READ input 
Use patterns instead of multiple instructions
Add buffer id to asm string

https://reviews.llvm.org/D22650

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278749 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-08-15 21:38:30 +00:00
Matt Arsenault
40ca91a07a AMDGPU/R600: Replace barrier intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275870 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-07-18 18:34:59 +00:00
Jan Vesely
e2b4643334 AMDGPU/R600: Add implicitarg.ptr intrinsic 
Differential Revision: http://reviews.llvm.org/D21622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275024 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-07-10 21:20:29 +00:00
Tom Stellard
25cd212829 AMDGPU/R600: Add PatFrags for selecting the correct vtx id for loads 
This moves of the r600 logic out of isGlobalLoad() and into the
TableGen files.

Differential Revision: http://reviews.llvm.org/D21710

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274527 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-07-05 00:12:51 +00:00
Jan Vesely
a8d19bb081 AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2) 
Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269473 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-05-13 20:39:16 +00:00
Matt Arsenault
3d679fa973 AMDGPU: Remove 24-bit intrinsics 
The known bit matching code seems to work reasonably well,
so these shouldn't really be needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@259180 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-01-29 10:05:16 +00:00
Matt Arsenault
3e81c4eb9a AMDGPU: Remove random TGSI intrinsic 
I don't think this was ever used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258514 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-01-22 18:42:44 +00:00
Matt Arsenault
f12a12cd25 AMDGPU: Pattern match ffbh pattern to instruction. 
The hardware instruction's output on 0 is -1 rather than 32.
Eliminate a test and select to -1. This removes an extra instruction
from the compatability function with HSAIL's firstbit instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257352 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-01-11 17:02:00 +00:00
Tom Stellard
7fe09ce82f AMDGPU: Add MEM_RAT STORE_TYPED. 
v2: Add test (Matt).
    Fix capitalization of isEOP (Matt).
    Move pattern to class parameter (Matt).
    Make the instruction available to Cayman (Matt).
    Change name from MEM_RAT WRITE_TYPED to MEM_RAT STORE_TYPED.

Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249042 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-10-01 17:51:34 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-13 03:28:10 +00:00