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Author SHA1 Message Date
Craig Topper
9b1b25f063 Tidy up spacing in some tablegen outputs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 06:52:47 +00:00
Craig Topper
769bbfd951 Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 05:20:24 +00:00
Bill Wendling
90e7d4f6f0 Reformatting. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153928 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 03:56:52 +00:00
Bill Wendling
cbece8c2a6 As Eric pointed out, even a Debug build should be equal. Leave the flag that can turn off comparisons though. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153927 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 03:27:43 +00:00
Akira Hatanaka
9dd16d41a2 Revert r153924. Delete test/MC/Disassembler/Mips and lib/Target/Mips/Disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153926 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 03:01:13 +00:00
Akira Hatanaka
02365945a6 Revert r153924. There were buildbot failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 02:51:09 +00:00
Akira Hatanaka
885020a7a7 MIPS disassembler support. 
Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 02:20:58 +00:00
Andrew Trick
5aeda3f076 Cleanup set_union usage. The same thing but a bit cleaner now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153922 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 01:35:52 +00:00
Andrew Trick
f1275959b2 Use std::set_union instead of nasty custom code. 
I just noticed Jakob's examples of the proper application of
std::set... routines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153918 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 00:47:23 +00:00
Eric Christopher
6126a1e189 Add a line number for the scope of the function (starting at the first 
brace) so that we get more accurate line number information about the
declaration of a given function and the line where the function
first starts.

Part of rdar://11026482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153916 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 00:43:49 +00:00
Pete Cooper
2e267ae7b8 Fixes to r153903. Added missing explanation of behaviour when the VirtRegMap is NULL. Also changed it in this case to just avoid updating the map, but live ranges or intervals will still get updated and created 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153914 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-03 00:28:46 +00:00
Bill Wendling
1adc215ddc Compare the .o files only for release builds. Add an option to bypass the comparison altogether. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153909 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 23:27:43 +00:00
Pete Cooper
789d5d85ba Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153906 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 22:44:18 +00:00
Rafael Espindola
1c8cf21d0c Make dominatedBySlowTreeWalk private and assert cases handled by the caller. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153905 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 22:37:54 +00:00
Jakob Stoklund Olesen
e3b23cde80 Allocate virtual registers in ascending order. 
This is just the fallback tie-breaker ordering, the main allocation
order is still descending size.

Patch by Shamil Kurmangaleev!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153904 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 22:30:39 +00:00
Pete Cooper
8a06af9669 Refactored the LiveRangeEdit interface so that MachineFunction, TargetInstrInfo, MachineRegisterInfo, LiveIntervals, and VirtRegMap are all passed into the constructor and stored as members instead of passed in to each method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153903 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 22:22:53 +00:00
Bill Wendling
3197b4453d Add an option to turn off the expensive GVN load PRE part of GVN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153902 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 22:16:50 +00:00
Owen Anderson
29f60f359b Add predicates for checking whether targets have free FNEG and FABS operations, and prevent the DAGCombiner from turning them into bitwise operations if they do. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153901 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 22:10:29 +00:00
Lang Hames
be9fe49b17 During two-address lowering, rescheduling an instruction does not untie 
operands. Make TryInstructionTransform return false to reflect this.
Fixes PR11861.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153892 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 19:58:43 +00:00
Rafael Espindola
ce167840b2 No need to run llvm-as. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153890 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 19:44:20 +00:00
Akira Hatanaka
a551a48402 Initial 64 bit direct object support. 
This patch allows llvm to recognize that a 64 bit object file is being produced
and that the subsequently generated ELF header has the correct information.

The test case checks for both big and little endian flavors.

Patch by Jack Carter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153889 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 19:25:22 +00:00
Hal Finkel
70272aac56 The binutils for the IBM BG/P are too old to support CFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153886 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 19:09:04 +00:00
Hal Finkel
a47406c442 Add triple support for the IBM BG/P and BG/Q supercomputers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153882 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 18:31:33 +00:00
Eric Christopher
60777d8eaf Turn on the accelerator tables for Darwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153880 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 17:58:52 +00:00
Stepan Dyatkovskiy
aad9c3f17a Fast fix for PR12343: 
http://llvm.org/bugs/show_bug.cgi?id=12343

We have not trivial way for splitting edges that are goes from indirect branch. We can do it with some tricks, but it should be additionally discussed. And it is still dangerous due to difficulty of indirect branches controlling.

Fix forbids this case for unswitching.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153879 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 17:16:45 +00:00
Roman Divacky
466958c2a0 Implement the SVR4 byval alignment for aggregates. Fixing a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153876 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 15:49:30 +00:00
Silviu Baranga
545b962f15 Second part for the 153874 one 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153875 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 15:46:46 +00:00
Silviu Baranga
50ac2e9229 Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 15:20:39 +00:00
Rafael Espindola
5004e9849a Add missing 'd'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153872 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 13:02:57 +00:00
Bill Wendling
8ba9405c5c Hack the hack. If we have a situation where an ASM object is defined but isn't 
reflected in the LLVM IR (as a declare or something), then treat it like a data
object.

N.B. This isn't 100% correct. The ASM parser should supply more information so
that we know what type of object it is, and what attributes it should have.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153870 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 10:01:21 +00:00
Benjamin Kramer
94338594ef Emit the asm writer's mnemonic table with SequenceToOffsetTable. 
This way we can get AVX v-prefixed instructions tail merged with the normal insns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153869 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 09:13:46 +00:00
Benjamin Kramer
c97ef618d2 Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter. 
All implementations used the same code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 08:32:38 +00:00
Craig Topper
fab3f7ee6f Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153865 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 07:48:39 +00:00
Nadav Rotem
44b5e6de8c Optimizing swizzles of complex shuffles may generate additional complex shuffles. 
Do not try to optimize swizzles of shuffles if the source shuffle has more than
a single user, except when the source shuffle is also a swizzle.






git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153864 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 07:11:12 +00:00
Craig Topper
7c0b3c1fb6 Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 07:01:04 +00:00
Eric Christopher
79e22d8c45 Fix CXXFLAGS for huge_val.m4. 
Patch by Jeremy Huddleston!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153862 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 06:54:01 +00:00
Craig Topper
17463b3ef1 Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 06:09:36 +00:00
Bill Wendling
1fcbca05db It could come about that we parse the inline ASM before we get a potential 
definition for it. In that case, we want to wait for the potential definition
before we create a symbol for it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153859 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 03:33:31 +00:00
Craig Topper
a4bd58b0f0 Use SequenceToOffsetTable to generate instruction name table for AsmWriter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153857 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-02 00:47:39 +00:00
Chandler Carruth
caa2c40a57 Start cleaning up the InlineCost class. This switches to sentinel values 
rather than a bitfield, a great suggestion by Chris during code review.

There is still quite a bit of cruft in the interface, but that requires
sorting out some awkward uses of the cost inside the actual inliner.

No functionality changed intended here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153853 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 22:44:09 +00:00
Hal Finkel
b66e943d4c Fix some 80-col. violations I introduced with the A2 PPC64 core. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153852 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 21:20:14 +00:00
Hal Finkel
19aa2b5015 Enable prefetch generation on PPC64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153851 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 20:08:17 +00:00
Hal Finkel
730acfb413 Add LdStSTD* itin. for the PPC64 A2 core. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153850 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 20:08:08 +00:00
Nadav Rotem
4ac9081c71 This commit contains a few changes that had to go in together. 
1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
   (and also scalar_to_vector).

2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src).
   Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B))

3. Optimize swizzles of shuffles:  shuff(shuff(x, y), undef) -> shuff(x, y).

4. Fix an X86ISelLowering optimization which was very bitcast-sensitive.

Code which was previously compiled to this:

movd    (%rsi), %xmm0
movdqa  .LCPI0_0(%rip), %xmm2
pshufb  %xmm2, %xmm0
movd    (%rdi), %xmm1
pshufb  %xmm2, %xmm1
pxor    %xmm0, %xmm1
pshufb  .LCPI0_1(%rip), %xmm1
movd    %xmm1, (%rdi)
ret

Now compiles to this:

movl    (%rsi), %eax
xorl    %eax, (%rdi)
ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153848 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 19:31:22 +00:00
Lang Hames
16d6eae082 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153846 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 19:27:25 +00:00
Hal Finkel
3f31d492a5 Set the default PPC node scheduling preference to ILP (for the embedded cores). 
The 440 and A2 cores have detailed itineraries, and this allows them to be
fully used to maximize throughput.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153845 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 19:23:08 +00:00
Hal Finkel
800125f3a3 Add ppc440 itin. entries for LdStSTD* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153844 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 19:23:04 +00:00
Hal Finkel
97c9d4c64c Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores. 
Post-RA scheduling gives a significant performance improvement on
the embedded cores, so turn it on. Using full anti-dep. breaking is
important for FP-intensive blocks, so turn it on (just on the
embedded cores for now; this should also be good on the 970s because
post-ra scheduling is all that we have for now, but that should have
more testing first).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153843 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 19:22:57 +00:00
Hal Finkel
4d989ac93c Add instruction itinerary for the PPC64 A2 core. 
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 19:22:40 +00:00
Craig Topper
413b2e7539 Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153841 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-01 18:14:14 +00:00