Commit Graph

10259 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
e7917bb207 Use COPY for fast-isel bitconvert, but don't create cross-class copies.
This doesn't change the behavior of SelectBitcast for X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 05:16:54 +00:00
Rafael Espindola
cbeeae23c3 Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 04:01:49 +00:00
Jakob Stoklund Olesen
e797e0c864 Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.
This assumes that the registers can be copied which is probably a safe
assumption.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108070 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 03:31:05 +00:00
Jakob Stoklund Olesen
5127f79913 Use COPY in FastISel everywhere it is safe and trivial.
The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108069 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 03:31:00 +00:00
Jakob Stoklund Olesen
1e1098c6f3 Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108062 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 22:42:59 +00:00
Jakob Stoklund Olesen
c0075cce7c Only collect subreg extracting copies for later coalescing.
This also avoids fatal copies from physregs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 22:42:53 +00:00
Dan Gohman
a8dab36f3d Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;
if a block is split (by a custom inserter), the insert point may be in a
different block than it was originally. This fixes 32-bit llvm-gcc
bootstrap builds, and I haven't been able to reproduce it otherwise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 22:42:31 +00:00
Jakob Stoklund Olesen
92c1f72c54 Emit COPY instructions instead of using copyRegToReg in InstrEmitter,
ScheduleDAGEmit, TwoAddressLowering, and PHIElimination.

This switches the bulk of register copies to using COPY, but many less used
copyRegToReg calls remain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 19:08:25 +00:00
Dan Gohman
3cd26a2909 Insert IMPLICIT_DEF instructions at the current insert position, not
at the end of the block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108045 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 13:55:45 +00:00
Dan Gohman
84023e0fbe Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 09:00:22 +00:00
Devang Patel
7a029b6d7e Update DBG_VALUE to refer appropriate stack slot in case of a spill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108023 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 21:48:31 +00:00
Jakob Stoklund Olesen
8ea324093c Fix small bug in isMoveInstr -> COPY translation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:55:49 +00:00
Jakob Stoklund Olesen
1f32340d95 Automatically fold COPY instructions into stack load/store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:43:13 +00:00
Jakob Stoklund Olesen
90fc0f4443 Remat uncoalescable COPY instrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108010 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:43:05 +00:00
Bill Wendling
8886c495a3 Clarify what mysterious check means.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 19:44:12 +00:00
Dan Gohman
aa7426070d Fix MachineLICM to actually visit inner loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 18:49:45 +00:00
Jakob Stoklund Olesen
e05442d508 Change TII::foldMemoryOperand API to require the machine instruction to be
inserted in a MBB, and return an already inserted MI.

This target API change is necessary to allow foldMemoryOperand to call
storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot
reference in a target independent way.

The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait
until COPY folding is actually implemented. Most targets only fold copies and
won't need to specialize this hook at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 17:29:08 +00:00
Bob Wilson
02266e29f9 --- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 16:37:18 +00:00
Gabor Greif
03f09a3e32 cache result of operator*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 16:08:33 +00:00
Jakob Stoklund Olesen
8154f96f44 Avoid creating %physreg:subidx operands in SimpleRegisterCoalescing::RemoveCopyByCommutingDef.
This fixes PR7602.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107957 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 05:56:21 +00:00
Jakob Stoklund Olesen
846a31881f Deal with a few remaining spots that assume physical registers have live intervals.
This fixes PR7601.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 04:35:38 +00:00
Jakob Stoklund Olesen
665eb12466 Fix broken isCopy handling in TrimLiveIntervalToLastUse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 01:27:21 +00:00
Jakob Stoklund Olesen
1769cccfc8 Handle COPY in VirtRegRewriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 01:27:19 +00:00
Dan Gohman
bf87e24917 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:39:23 +00:00
Bob Wilson
f1d93ca920 Reenable DAG combining for vector shuffles. It looks like it was temporarily
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:12 +00:00
Stuart Hastings
99cfb69f17 Reverting r107918 and r107919. Radar 8063111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 23:25:39 +00:00
Jakob Stoklund Olesen
21e9445952 Revert "Fix broken isCopy handling in TrimLiveIntervalToLastUse"
This reverts commit 107921. It broke the clang self host.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107926 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:52:47 +00:00
Devang Patel
0afbf23453 Relax assertion. In optimized code, it is possible that first instruction is coming from a inlined function.
This fixes PR7596 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:39:20 +00:00
Bill Wendling
c930cbcada Extension of r107506. Make sure that we don't mark a function as having a call
if the inline ASM doesn't need a stack frame.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:38:02 +00:00
Jakob Stoklund Olesen
7cc4f9cd28 Fix broken isCopy handling in TrimLiveIntervalToLastUse
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:30:38 +00:00
Stuart Hastings
c0e2639a34 Fix decl/def debug info for template functions. Radar 8063111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 22:28:59 +00:00
Devang Patel
ca76f6f57c Reuse DIEInteger for 1. This is frequently used while emitting an attribute using dwarf::DW_FORM_flag form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 20:10:35 +00:00
Jim Grosbach
ed903d746d Clean up scavengeRegister() a bit to prefer available regs, which allows
the simplification of frame index register scavenging to not have to check
for available registers directly and instead just let scavengeRegister()
handle it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:49:26 +00:00
Jakob Stoklund Olesen
0bc25f4040 Convert EXTRACT_SUBREG to COPY when emitting machine instrs.
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen
5c00e07795 Remove references to INSERT_SUBREG after de-SSA.
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 16:40:15 +00:00
Benjamin Kramer
cde51108de Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107868 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 12:09:56 +00:00
Jakob Stoklund Olesen
3651d92d91 Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs.
This target hook is intended to replace copyRegToReg entirely, but for now it
calls copyRegToReg.

Any remaining calls to copyRegToReg wil be replaced by COPY instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 05:01:41 +00:00
Dan Gohman
f595141525 Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 01:00:56 +00:00
Jim Grosbach
d9642faf7c When processing frame index virtual registers, consider all available registers
(if there are any) and use the one which remains available for the longest
rather than just using the first one. This should help enable better re-use
of the loaded frame index values. rdar://7318760



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107847 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 00:38:54 +00:00
Dan Gohman
49dcb0f9ec Don't forward-declare registers for static allocas, which we'll
prefer to materialize as local constants. This fixes the clang
bootstrap abort.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 23:52:58 +00:00
Dan Gohman
61b7cea126 Fix -fast-isel-abort to check the right instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 23:47:25 +00:00
Devang Patel
8aa61477e3 One MDNode may be used to create regular DIE as well as abstract DIE.
Keep track of abstract subprogram DIEs. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:20:57 +00:00
Evan Cheng
bcc8017c73 Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:15:37 +00:00
Dan Gohman
5c480432b5 Not all custom inserters create new basic blocks. If the inserter
didn't create a new block, don't reset the insert position.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107813 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 21:18:22 +00:00
Devang Patel
869aa463c8 Rename couple of maps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 20:49:57 +00:00
Devang Patel
6140962aba 80 cols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107807 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 20:12:52 +00:00
Dan Gohman
4df83ed159 Implement bottom-up fast-isel. This has the advantage of not requiring
a separate DCE pass over MachineInstrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107804 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 19:20:32 +00:00
Dan Gohman
f423a69839 Add X86FastISel support for return statements. This entails refactoring
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:32:53 +00:00
Dan Gohman
5fc3da0665 Update the insert position after scheduling, which may change the
position when emitting multiple blocks when executing a custom
inserter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:22:13 +00:00
Devang Patel
cc87bfb59b Update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 18:18:18 +00:00