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Author SHA1 Message Date
Reid Kleckner
894728211d Update the docs for debugging JITed code with GDB. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 20:16:45 +00:00
Devang Patel
6140962aba 80 cols. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107807 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 20:12:52 +00:00
Dan Gohman
4df83ed159 Implement bottom-up fast-isel. This has the advantage of not requiring 
a separate DCE pass over MachineInstrs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107804 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 19:20:32 +00:00
Dan Gohman
f423a69839 Add X86FastISel support for return statements. This entails refactoring 
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 18:32:53 +00:00
Bruno Cardoso Lopes
ced9ec9bac Add AVX AES instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 18:24:20 +00:00
Dan Gohman
5fc3da0665 Update the insert position after scheduling, which may change the 
position when emitting multiple blocks when executing a custom
inserter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 18:22:13 +00:00
Devang Patel
cc87bfb59b Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107796 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 18:18:18 +00:00
Dan Gohman
643fffe429 Fix debugging strings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107795 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 17:28:45 +00:00
Duncan Sands
2b48c33936 Issue the warning about being slow whenever optimization is disabled, 
and not just for Debug+Asserts builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 16:48:16 +00:00
Dan Gohman
eabaed26c3 Give FunctionLoweringInfo an MBB member, avoiding the need to pass it 
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 16:47:08 +00:00
Dan Gohman
a4160c3434 Simplify FastISel's constructor by giving it a FunctionLoweringInfo 
instance, rather than pointers to all of FunctionLoweringInfo's
members.

This eliminates an NDEBUG ABI sensitivity.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 16:29:44 +00:00
Dan Gohman
4c3fd9f92f Move FunctionLoweringInfo.h out into include/llvm/CodeGen. This will 
allow target-specific fast-isel code to make use of it directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107787 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 16:01:37 +00:00
Dan Gohman
c9403659a9 Split the SDValue out of OutputArg so that SelectionDAG-independent 
code can do calling-convention queries. This obviates OutputArgReg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 15:54:55 +00:00
Chris Lattner
29269d03af add some triple for minix, patch by Kees van Reeuwijk from PR7582 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107785 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 15:52:27 +00:00
Dan Gohman
ce5172098d Move ArgFlagsTy, OutputArg, and InputArg out of SelectionDAGNodes.h and 
into a new header, TargetCallingConv.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107782 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 15:28:42 +00:00
Dan Gohman
2f2b0abbac Move CallingConvLower.cpp out of the SelectionDAG directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107781 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 15:15:27 +00:00
Jakob Stoklund Olesen
fcb4ccd7aa Fix more places assuming subregisters have live intervals 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 14:41:22 +00:00
Gabor Greif
e3c5502263 adapt condition for changed default build mode 
who knows how to cover Asserts or Debug separately
please do not hesitate to extend this

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107779 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 14:37:04 +00:00
Dan Gohman
d463a74464 Add a getFirstNonPHI utility function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107778 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 14:33:51 +00:00
Dan Gohman
b8c86a010c Minore code simplification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107777 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 14:30:04 +00:00
Dan Gohman
9e86f4364b Remove interprocedural-basic-aa and associated code. The AliasAnalysis 
interface needs implementations to be consistent, so any code which
wants to support different semantics must use a different interface.
It's not currently worthwhile to add a new interface for this new
concept.

Document that AliasAnalysis doesn't support cross-function queries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107776 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 14:27:09 +00:00
Dan Gohman
46151f1764 Add Debug+Asserts and Release+Asserts to svn:ignore properties. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107775 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 14:12:28 +00:00
Gabor Greif
6418cb3f4b typo in comment, regeneration not necessary 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107774 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 13:58:46 +00:00
Gabor Greif
274fefdd96 conditionalize by CallInst::ArgOffset 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107767 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 10:34:03 +00:00
Gabor Greif
392a8867bb conditionalize on CallInst::ArgOffset 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107766 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 09:43:45 +00:00
Gabor Greif
dc4f391773 minor cosmetic changes that happened to sit in my tree 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107764 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 09:29:07 +00:00
Duncan Sands
8246adc1f0 Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts" 
builds to "Release".  The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts.  The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown).  This will bring them
in line with MacOS releases, which ship with assertions disabled.  It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107758 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 07:48:00 +00:00
Bruno Cardoso Lopes
4f6bdf9042 Add AVX SSE4.2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107752 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
332fce49e3 Use only one multiclass to pinsrq instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107750 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
5e9fa98523 Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107749 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 01:33:38 +00:00
Bruno Cardoso Lopes
09df2ae0d0 Add AVX SSE4.1 insertps, ptest and movntdqa instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107747 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
3c14822312 Add AVX SSE4.1 extractps and pinsr instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107746 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 01:01:13 +00:00
Jakob Stoklund Olesen
4b76ffc1ff Revert "Remove references to INSERT_SUBREG after de-SSA" r107725. 
Buildbot breakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107744 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 00:32:25 +00:00
Bob Wilson
78dfbc380d Also use REG_SEQUENCE for VTBX instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107743 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 00:08:54 +00:00
Jim Grosbach
e97f968a69 Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where 
they've been tested to work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107742 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 00:07:57 +00:00
Bruno Cardoso Lopes
4fd32db6a6 Add AVX SSE4.1 Extract Integer instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107740 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-07 00:07:24 +00:00
Jim Grosbach
c66e150b2c By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather 
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107734 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:44:52 +00:00
Jakob Stoklund Olesen
d3b376b448 Remove references to INSERT_SUBREG after de-SSA 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107732 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:40:35 +00:00
Bob Wilson
d491d6ecd2 Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be 
allocated to consecutive registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107730 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:36:25 +00:00
Dale Johannesen
e2b448c208 Accept RIP-relative symbols with 'i' constraint, and 
print the (%rip) only if the 'a' modifier is present.
PR 7528.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107727 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:27:00 +00:00
Jakob Stoklund Olesen
ed2185e171 Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass. 
INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107726 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:26:25 +00:00
Jakob Stoklund Olesen
fca3a25fed Track defs for all aliases in NEONMoveFix. 
This means that an instruction defining an S register will affect the domain of
the parent D register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107725 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:26:23 +00:00
Bruno Cardoso Lopes
ee94e8297e Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:15:17 +00:00
Dale Johannesen
e6fd5ad6f4 Make test not hang waiting for input. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107721 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:06:58 +00:00
Bruno Cardoso Lopes
36869b69b0 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
0106680a2c Fix comment from previous patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107717 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes
07de40629f Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 22:36:24 +00:00
Dan Gohman
c9af33c685 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext. 
SelectBasicBlock doesn't needs its BasicBlock argument.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 22:19:37 +00:00
Devang Patel
0d881dabc1 Propagate debug loc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 22:08:15 +00:00
Bob Wilson
f967ca0eaf Represent NEON load/store alignments in bytes, not bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107701 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-06 21:26:18 +00:00