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62 Commits

Author SHA1 Message Date
Craig Topper
0ce91864ce [AVX-512] Give priority to EVEX encoded scalar FMA instructions when we have FMA, AVX512 and no VLX. 
We were giving priority if VLX was enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298046 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-17 06:10:37 +00:00
Craig Topper
1230bb045a [X86][FMA4] Remove isCommutable from FMA4 scalar intrinsics. They aren't commutable as operand 0 should pass its upper bits through to the output. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288011 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-27 21:37:04 +00:00
Craig Topper
a4203c3506 [X86][FMA] Add missing Predicates qualifier around scalar FMA intrinsic patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288010 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-11-27 21:37:02 +00:00
Craig Topper
91e5e5818d [X86] Create a new instruction format to handle MemOp4 encoding. This saves one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279423 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-08-22 07:38:45 +00:00
Craig Topper
1314c16889 [X86] Remove CustomInserter for FMA3 instructions. Looks like since we got full commuting support for FMAs after this was added, the coalescer can now get this right on its own. 
Differential Revision: https://reviews.llvm.org/D22799

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276987 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-07-28 15:28:56 +00:00
Craig Topper
f2a1f86928 [X86] Make the FMA3 instruction names consistent between VEX and EVEX encoded versions. 
This places the 132/213/231 form number in front of the SS/SD/PS/PD. Move the Y for 256-bit versions to be after the PS/PD. Change the AVX512 scalar forms to include a Z in the their name. This new format should be consistent with the general naming of instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276559 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-07-24 08:26:38 +00:00
Vyacheslav Klochkov
a23ddb7891 X86-FMA3: Defined the ExeDomain property for Scalar FMA3 opcodes. 
Reviewer: Simon Pilgrim.
Differential Revision: http://reviews.llvm.org/D15317


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255080 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-12-09 00:12:13 +00:00
Simon Pilgrim
fbbab8b959 [X86][FMA4] Explicitly set the domain of FMA4 float/double scalar instructions 
Both were defaulting to the float domain - now matches the packed instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254841 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-12-05 07:07:42 +00:00
Vyacheslav Klochkov
d9357adaa7 X86-FMA3: Improved/enabled the memory folding optimization for scalar loads 
generated for _mm_losd_s{s,d}() intrinsics and used in scalar FMAs generated 
for FMA intrinsics _mm_f{madd,msub,nmadd,nmsub}_s{s,d}().

Reviewer: David Kreitzer
Differential Revision: http://reviews.llvm.org/D14762



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254140 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-11-26 07:45:30 +00:00
Sanjay Patel
d2cf0a31d0 fix typo; NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254069 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-11-25 15:33:36 +00:00
Vyacheslav Klochkov
c81095daa7 X86-FMA3: Implemented commute transformations FMA*_Int instructions. 
It made it possible to apply the memory folding optimization for the 2nd
operand of FMA*_Int instructions.

Reviewer: Quentin Colombet
Differential Revision: http://reviews.llvm.org/D14550


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252973 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-11-13 00:07:35 +00:00
Andrew Kaylor
91950eea55 Improved the operands commute transformation for X86-FMA3 instructions. 
All 3 operands of FMA3 instructions are commutable now.

Patch by Slava Klochkov

Reviewers: Quentin Colombet(qcolombet), Ahmed Bougacha(ab).

Differential Revision: http://reviews.llvm.org/D13269



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252335 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-11-06 19:47:25 +00:00
Andrew Kaylor
80a2456665 Created new X86 FMA3 opcodes (FMA*_Int) that are used now for lowering of scalar FMA intrinsics. 
Patch by Slava Klochkov 

The key difference between FMA* and FMA*_Int opcodes is that FMA*_Int opcodes are handled more conservatively. It is illegal to commute the 1st operand of FMA*_Int instructions as the upper bits of scalar FMA intrinsic result must be taken from the 1st operand, but such commute transformation would change those upper bits and invalidate the intrinsic's result.

Reviewers: Quentin Colombet, Elena Demikhovsky

Differential Revision: http://reviews.llvm.org/D13710



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252060 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-11-04 18:10:41 +00:00
Michael Kuperstein
8ffbb68a86 [X86] When pattern-matching scalar FMA3 intrinsics, don't re-arrange the first and second operands. 
The semantics of the scalar FMA intrinsics are that the high vector elements are copied from the first source.
The existing pattern switches src1 and src2 around, to match the "213" order, which ends up tying the original src2 to the dest. Since the actual scalar fma3 instructions copy the high elements from the dest register, the wrong values are copied.

This modifies the pattern to leave src1 and src2 in their original order.

Differential Revision: http://reviews.llvm.org/D9908

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238131 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-25 12:35:25 +00:00
Craig Topper
c0dae440e6 Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222801 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-26 00:46:26 +00:00
Quentin Colombet
97e15a8309 [X86] Selectively mark the FMA variants inside a family as isCommutable. 
Given a FMA family (e.g., 213, 231), not all the variants (i.e., register or
memory) are commutable.
E.g., for the 213 family (with the syntax src1, src2, src3):
fmaXXX213 A, B, reg3/mem3 == fmaXXX213 B, A, reg3/mem3

Now consider the 231 family:
fmaXXX231 A, B, reg3 == fmaXXX231 A, reg3, B
But
fmaXXX231 A, B, mem3 != fmaXXX231 A, mem3, B
Indeed, mem3 cannot be the second argument of the memory variant of fmaXXX231.

Working on a reduced test case!

<rdar://problem/16800495>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208252 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-07 21:43:35 +00:00
Lang Hames
b1b4d08195 [X86] Make the VFMA*231 variants commutable and relax the alignment restrictions 
on FMA3 memory operands. FMA3 instructions are VEX encoded, so they can load
from unaligned memory.

Testcase to follow, along with related patch.

<rdar://problem/16478629>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205472 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-02 22:06:16 +00:00
Lang Hames
051faa2cfa [X86] Only 213 FMA3 variants should be marked commutable. 
Commuting the 231 and 132 variants would swap addends and
multiplicands/multipliers, which isn't valid.

I'm still trying to reduce a decent test case for this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200792 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-04 19:42:47 +00:00
Lang Hames
f96f832a3c Replace X86 FMA intrinsic pseduo-instructions with def pats. 
It looks like these pseudos were only used for pattern matching. Def pats are
the appropriate way to do that. As a bonus, these intrinsics will now have
memory operands folded properly, and better FMA3 variants selected where
appropriate (see r199933).

<rdar://problem/15611947>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200577 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-31 21:29:19 +00:00
Lang Hames
d8f4348cab Replace vfmaddxx213 instructions with their 231-type equivalents in accumulator 
loops. Writing back to the accumulator (231-type) allows the coalescer to
eliminate an extra copy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199933 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-23 20:23:36 +00:00
Craig Topper
527f132627 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-05 04:17:28 +00:00
Craig Topper
e625100c6a Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198323 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-02 17:28:14 +00:00
Craig Topper
92b4581953 Various x86 disassembler fixes. 
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191649 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 02:46:36 +00:00
Craig Topper
95838d5caf Remove alignment restrictions from FMA load folding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191136 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-21 05:58:59 +00:00
Craig Topper
29344a6349 Simplify nested strconcats in X86 td files since strconcat can take more than 2 arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172379 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-14 07:46:34 +00:00
Craig Topper
37cb8398c8 Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:30:22 +00:00
Craig Topper
9648782552 Fix execution domain for packed FMA4 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168417 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 08:08:21 +00:00
Craig Topper
cbf3daee0b Add explicit VEX_L tags to all 256-bit instructions. This will allow us to remove code from the code emitters that examined operands to set the L-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164202 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-19 06:06:34 +00:00
Craig Topper
dfb1e4babd Mark FMA4 instructions as commutable and add them to the folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163035 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 23:10:34 +00:00
Craig Topper
cb0848696d Mark FMA3 instructions as commutable so that the operands to the multiply part can be commuted. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163001 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 16:31:13 +00:00
Craig Topper
bf4043768c Add support for converting llvm.fma to fma4 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162999 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-31 15:40:30 +00:00
Craig Topper
fd49821c35 Convert FMA4 patterns to use target specific nodes instead of intrinsics to align with FMA3. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162829 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-29 07:18:25 +00:00
Jakob Stoklund Olesen
3d2a2d1217 Remove more mayLoad workarounds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162556 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 14:43:22 +00:00
Craig Topper
0e292376d0 Custom lower FMA intrinsics to target specific nodes and remove the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162534 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 04:03:22 +00:00
Craig Topper
5f67d94697 Cleanup the scalar FMA3 definitions. Add patterns to fold loads with scalar forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162260 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 07:11:11 +00:00
Craig Topper
e4b6189658 Merge FMA3 instructions with and without patterns into single classes using null_frag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162257 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 05:56:45 +00:00
Craig Topper
75d8ad461f Remove FMA3 intrinsic instructions in favor of patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162194 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-20 06:21:25 +00:00
Craig Topper
f4eb22a01c Use correct intrinsic for 256-bit VFMSUBADDPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162193 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-20 06:03:04 +00:00
Craig Topper
8f9c7417b4 Remove trailing white space and tab characters. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162192 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-19 23:37:46 +00:00
Elena Demikhovsky
1503aba4a0 Added FMA functionality to X86 target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 12:06:00 +00:00
Craig Topper
caea5e28b2 Add intrinsic forms for FMA instructions to opcode folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157917 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 07:46:16 +00:00
Craig Topper
529ce07c5f Rename fma4 intrinsics to just fma since they are now used for both FMA4 and FMA3. Autoupgrade support coming in a separate commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 07:26:46 +00:00
Craig Topper
57ae246a6a Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit loads to match instruction behavior. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157895 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 01:40:43 +00:00
Craig Topper
60dda38008 Add neverHasSideEffects and mayLoad to FMA3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157894 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-03 00:30:49 +00:00
Craig Topper
3a8172ad8d Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157804 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 06:07:48 +00:00
Craig Topper
d9567223e8 Tidy up. Remove trailing spaces and fix the worst of the 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157799 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-01 05:24:29 +00:00
Elena Demikhovsky
177cf1e1a3 Added FMA3 Intel instructions. 
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 09:20:20 +00:00
Jia Liu
44de83a7f6 some comment fix for X86 and ARM 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150902 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-19 02:03:36 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Craig Topper
193cf04f5b Mark scalar FMA4 instructions as ignoring the VEX.L bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147602 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-05 08:56:10 +00:00