138503 Commits

Author SHA1 Message Date
Mehdi Amini
a2d3e0354c BitcodeWriter: fix emission of invoke when calling a var-arg function with operand bundles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281940 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 21:27:04 +00:00
Evgeniy Stepanov
050e90399c Misleading comments of SplitBlockAndInsertIfThenElse in BasicBlockUtils.h
The comments of SplitBlockAndInsertIfThenElse say the SplitBefore instruction will stay in the old block.
But according to the implementation(split the block at SplitBefore by using splitBasicBlock), the SplitBefore will be moved to the new block.

This patch fixes the comments.

Patch by Zhe Yu Wu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281939 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 21:26:05 +00:00
Simon Pilgrim
4f6fc26807 [X86][SSE] Updated vector abs tests
Renamed and added v2i64 / v4i64 tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281937 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 20:50:35 +00:00
Kostya Serebryany
b3d4112198 [libFuzzer] use sleep() instead of std::this_thread::sleep_for to avoid coverage from instrumented libc++
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281933 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 20:32:34 +00:00
Dehao Chen
ddeacc711a Handle early inline for hot callsites that reside in the same basic block.
Summary: Callsites in the same basic block should share the same hotness. This patch checks for the hottest callsite in the same basic block, and use the hotness for all callsites in that basic block for early inline decisions. It also fixes the test to add "-S" so theat the "CHECK-NOT" is actually checking the content.

Reviewers: dnovillo

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24734

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281927 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 18:38:14 +00:00
Quentin Colombet
d809745696 [RegisterBankInfo] Avoid heap allocation in most cases.
The OperandsMapper class is used heavy in RegBankSelect and each
instantiation triggered a heap allocation for the array of operands.
Instead, use a SmallVector with a big enough size such that most of the
cases do not have to use dynamically allocated memory.

This improves the compile time of the RegBankSelect pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281916 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 17:33:55 +00:00
Matthias Braun
b0731963da LiveRangeCalc: Fix reporting of invalid vreg usage in liveness calculation
Machine programs need a definition of each vreg before reaching a use
(the definition may come from an IMPLICIT_DEF instruction). This class
of errors is not detected by the MachineVerifier because of efficiency
concerns. LiveRangeCalc used to report these problems, make it do that
again (followup to r279625).

Also use report_fatal_error() instead of llvm_unreachable() as the error
reporting is only present in asserts build anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281914 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 16:49:45 +00:00
Dehao Chen
ba3d957955 Only set branch weight during sample pgo annotation when max_weight of the branch is non-zero. Otherwise use default static profile to set branch probability.
Summary: It does not make sense to set equal weights for all unkown branches as we have static branch prediction available.

Reviewers: dnovillo

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24732

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281912 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 16:33:41 +00:00
Dehao Chen
625183db5a Use call target count to derive the call instruction weight
Summary: The call target count profile is directly derived from LBR branch->target data. This is more reliable than instruction frequency profiles that could be moved across basic block boundaries. This patches uses call target count profile to annotate call instructions.

Reviewers: davidxl, dnovillo

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24410

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281911 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 16:06:37 +00:00
Etienne Bergeron
b87b0d3795 [asan] Support dynamic shadow address instrumentation
Summary:
This patch is adding the support for a shadow memory with
dynamically allocated address range.

The compiler-rt needs to export a symbol containing the shadow
memory range.

This is required to support ASAN on windows 64-bits.

Reviewers: kcc, rnk, vitalybuka

Subscribers: kubabrecka, dberris, llvm-commits, chrisha

Differential Revision: https://reviews.llvm.org/D23354

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281908 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 15:58:38 +00:00
Zachary Turner
781fb6ecc8 [Support] Add StringRef::withNullAsEmpty()
When porting large bodies of code from using const char*
to StringRef, it is helpful to be able to treat nullptr
as an empty string, since that it is often what it is used
to indicate in C-style code.

Differential Revision: https://reviews.llvm.org/D24697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281906 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 15:34:51 +00:00
Nico Weber
ebd2807ce8 Revert r281841, it does not work on Windows (PR30443).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281905 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 15:22:04 +00:00
Valery Pykhtin
d1be85dd3c [AMDGPU] Refactor VOPC instruction TD definitions
Differential Revision: https://reviews.llvm.org/D24546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281903 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 14:39:49 +00:00
Diana Picus
1494db60ab [AArch64] Fix encoding for lsl #12 in add/sub immediates
Whenever an add/sub immediate needs a fixup, we set that immediate field to zero,
which is correct, but we also set the shift bits to zero, which is not true for
instructions that use lsl #12. This patch makes sure that if lsl #12 was used,
it will appear in the encoding of the instruction.

Differential Revision: https://reviews.llvm.org/D23930

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281898 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 11:10:18 +00:00
Sam Kolton
21fcdfd73b [AMDGPU] Fix s_branch with -1 offset
Summary:
In case s_branch instruction target is itself backend should emit offset -1 but instead it emit 0.
'''
label:
    s_branch label  // should emit [0xff,0xff,0x82,0xbf]
'''

Tom, Matt: why are we adjusting fixup values in applyFixup() method instead of processFixup()? processFixup() is calling adjustFixupValue() but does nothing with its result.

Reviewers: vpykhtin, artem.tamazov, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl

Differential Revision: https://reviews.llvm.org/D24671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281896 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 10:20:55 +00:00
Keith Walker
383922dd5b Add @llvm.dbg.value entries for the phi node created by -mem2reg
When phi nodes are created in the -mem2reg phase, the @llvm.dbg.declare
entries are converted to @llvm.dbg.value entries at the place where the
store instructions existed. However no entry is created to describe
the resulting value of the phi node.

The effect of this is especially noticeable in for loops which have a
constant for the intial value; the loop control variable's location
would be described as the intial constant value in the loop body once
the -mem2reg optimization phase was run.

This change adds the creation of the @llvm.dbg.value entries to describe
variables whose location is the result of a phi node created in -mem2reg.

Also when the phi node is finally lowered to a machine instruction it
is important that the lowered "load" instruction is placed before the
associated DEBUG_VALUE entry describing the value loaded.

Differential Revision: https://reviews.llvm.org/D23715


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281895 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 09:49:30 +00:00
Oliver Stannard
8d46442503 [Thumb] Set correct initial mapping symbol for big-endian thumb
The initial mapping symbol state is set from the triple, but we only checked
for the little-endian thumb triple, so could end up with an ARM mapping symbol
for big-endian thumb.

Differential Revision: https://reviews.llvm.org/D24553



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281894 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 09:21:45 +00:00
Tim Northover
ab6de7f248 ARM: check alignment before transforming ldr -> ldm (or similar).
ldm and stm instructions always require 4-byte alignment on the pointer, but we
weren't checking this before trying to reduce code-size by replacing a
post-indexed load/store with them. Unfortunately, we were also dropping this
incormation in DAG ISel too, but that's easy enough to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281893 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 09:11:09 +00:00
Elena Demikhovsky
01736613c2 [X86 Codegen Test] Divided masked_memop into several files. NFC.
The masked_memop.ll became huge. I extracted AVX-512 specific tests into separate files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281892 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 08:58:43 +00:00
James Molloy
1a9f29f7eb [SimplifyCFG] Update (AND) IR flags when CSE'ing instructions
We were updating metadata but not IR flags. Because we pick an arbitrary instruction to be the CSE candidate, it comes down to luck (50% or less chance) if this results in broken codegen or not, which is why PR30373 which is actually not the fault of the commit it was bisected down to.

Fixes PR30373.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281889 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 08:23:08 +00:00
Craig Topper
d854787edd [X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when the input is not the output of an instruction.
SUBREG_TO_REG is supposed to indicate that the super register has been zeroed, but we can't prove that if we don't know where it came from.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281885 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 02:53:43 +00:00
Craig Topper
d5369d3bd4 [AVX-512] Add support for lowering fp_to_f16 and f16_to_fp when VLX is supported regardless of whether F16C is also supported.
Still need to add support for lowering using AVX512F when neither VLX or F16C is supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281884 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 02:53:37 +00:00
Vedant Kumar
764028eefa [llvm-cov] Emit a link to some documentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281883 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 02:15:59 +00:00
Vedant Kumar
1b70b5dcc9 [llvm-cov] Delete the NonCodeLines field, it was always dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281882 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 01:46:01 +00:00
Dean Michael Berris
916b3667a3 [XRay] ARM 32-bit no-Thumb support in LLVM
This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter.
This is one of 3 commits to different repositories of XRay ARM port. The other 2 are:

https://reviews.llvm.org/D23932 (Clang test)
https://reviews.llvm.org/D23933 (compiler-rt)

Differential Revision: https://reviews.llvm.org/D23931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281878 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 00:54:35 +00:00
Vedant Kumar
70b43c34b6 [llvm-cov] Teach the coverage exporter about instantiation coverage
While we're at it, re-use the logic from CoverageReport to compute
summaries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281877 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 00:38:29 +00:00
Vedant Kumar
a830753405 [llvm-cov] Make a helper method static for re-use (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281876 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 00:38:25 +00:00
Vedant Kumar
e17f26f066 [llvm-cov] Track function and instantiation coverage separately
These are distinct statistics which are useful to look at separately.

Example: say you have a template function "foo" with 5 instantiations
and only 3 of them are covered. Then this contributes (1/1) to the total
function coverage and (3/5) to the total instantiation coverage. I.e,
the old "Function Coverage" column has been renamed to "Instantiation
Coverage", and the new "Function Coverage" aggregates information from
the various instantiations of a function.

One benefit of making this switch is that the Line and Region coverage
columns will start making sense. Let's continue the example and assume
that the 5 instantiations of "foo" cover {2, 4, 6, 8, 10} out of 10
lines respectively. The new line coverage for "foo" is (10/10), not
(30/50).  The old scenario got confusing because we'd report that there
were more lines in a file than what was actually possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281875 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 00:38:23 +00:00
Vedant Kumar
40817d86f0 [llvm-cov] Don't recompute the 'Covered' field from *CoverageInfo (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281874 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 00:38:18 +00:00
Vedant Kumar
6360ab9da4 [llvm-cov] Make 'adjustColumnWidths' do less work
This drops some redundant calls to get{UniqueSourceFiles,
CoveredFunctions}. We can figure out the right column widths without
re-doing this expensive work.

This isn't NFC, but I don't want to check in another binary *.covmapping
file with long filenames in it. I tested this locally on a project with
some long filenames (FileCheck).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281873 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 00:38:16 +00:00
Vedant Kumar
c063c43a4e [llvm-cov] Drop another redundant 'No.' suffix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281872 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 00:38:14 +00:00
Vedant Kumar
7b1bb280cd [utils] Delete the 'check-coverage-regressions' script
In practice, it's way too noisy.

It's also a maintenance burden, since we apparently can't add tests for
it without breaking some Windows setups (see: D22692).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281871 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 00:38:11 +00:00
Dehao Chen
60489f476b Handle Invoke during sample profiler annotation: make it inlinable.
Summary: Previously we reline on inst-combine to remove inlinable invoke instructions. This causes trouble because a few extra optimizations are schedule early that could introduce too much CFG change (e.g. simplifycfg removes too much control flow). This patch handles invoke instruction in-place during sample profile annotation, so that we do not rely on instcombine to remove those invoke instructions.

Reviewers: davidxl, dnovillo

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281870 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 23:11:37 +00:00
Xinliang David Li
178b58d881 Extend title underline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281869 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 22:10:19 +00:00
Craig Topper
1b68ca9a47 [AVX-512] Don't lower CVTPD2PS intrinsics to ISD::FP_ROUND with an X86 rounding mode encoding in the second operand. This immediate should only be 0 or 1 and indicates if the truncation loses precision.
Also enhance an assert in SelectionDAG::getNode to flag this sort of problem in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281868 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 21:49:32 +00:00
Craig Topper
ae55aa08fe [AVX-512] Stop lowering avx512_mask_sqrt intrinsics to ISD:FSQRT with a second operand containing an X86 specific rounding mode encoding that doesn't belong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281867 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 21:49:28 +00:00
Kostya Serebryany
304a0b44f3 [libFuzzer] add -print_coverage=1 flag to print coverage directly from libFuzzer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281866 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 21:47:08 +00:00
Simon Pilgrim
b9ae8b034a Fix covered-switch-default warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281865 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 21:08:35 +00:00
Simon Pilgrim
08a3649b8b [CostModel][X86] Added scalar float op costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281864 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 21:01:20 +00:00
Simon Pilgrim
04a2b34a5a Rename tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281863 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 20:25:41 +00:00
Craig Topper
45d1e6d835 [X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281862 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 18:59:38 +00:00
Craig Topper
04863470fe [AVX-512] Add memory load patterns for the legacy SSE scalar fp to integer conversion intrinsics to be consistent across all intruction sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281861 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 18:59:36 +00:00
Craig Topper
4153ca5f87 [AVX-512] Remove COPY_TO_REGCLASS from a few patterns that already had the correct register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281860 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 18:59:33 +00:00
Xinliang David Li
760a2d0c51 Fix built bot failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281859 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 18:52:08 +00:00
Xinliang David Li
ab430229ee [Profile] Implement select instruction instrumentation in IR PGO
Differential Revision: http://reviews.llvm.org/D23727


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281858 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 18:34:07 +00:00
Elena Demikhovsky
305b3f3b5a [Loop Vectorizer] Consecutive memory access - fixed and simplified
Amended consecutive memory access detection in Loop Vectorizer.
Load/Store were not handled properly without preceding GEP instruction.

Differential Revision: https://reviews.llvm.org/D20789



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281853 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 13:56:08 +00:00
Simon Pilgrim
428ba8ee90 [X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp
With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations.

This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware).

While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions.

Differential Revision: https://reviews.llvm.org/D24343

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281852 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 12:45:23 +00:00
Elena Demikhovsky
868c6d1643 [Loop vectorizer] Simplified GEP cloning. NFC.
Simplified GEP cloning in vectorizeMemoryInstruction().
Added an assertion that checks consecutive GEP, which should have only one loop-variant operand.

Differential Revision: https://reviews.llvm.org/D24557



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281851 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 09:22:54 +00:00
Wei Mi
f54e133dd2 Change the order of the splitted store from high - low to low - high.
It is a trivial change which could make the testcase easier to be reused
for the store splitting in CodeGenPrepare.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281846 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 06:10:32 +00:00
Kostya Serebryany
2bed90363f [libFuzzer] use 'if guard' instead of 'if guard >= 0' with trace-pc; change the guard type to intptr_t; use separate array for 8-bit counters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281845 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 04:52:23 +00:00