Commit Graph

104433 Commits

Author SHA1 Message Date
Craig Topper
559127a46b [SimplifyCFG] Move a portion of an if statement that should already be implied to an assert
Summary: In this code we got to Dom by following the predecessor link of BB. So it stands to reason that BB should also show up as a successor of Dom's terminator right? There isn't a way to have the CFG connect in only one direction is there?

Reviewers: jmolloy, davide, mcrosier

Reviewed By: mcrosier

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D35025

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307276 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 16:29:43 +00:00
Craig Topper
8e1b81f030 [InstCombine] Change helper method to a file local static method. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307275 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 16:24:23 +00:00
Craig Topper
5e02f67654 [InstCombine] Clarify comment to mention other transform that it does. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307274 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 16:24:22 +00:00
Craig Topper
afbb3e0e90 [InstCombine] Add single use checks to SimplifyBSwap to ensure we are really saving instructions
Bswap isn't a simple operation so we need to make sure we are really removing a call to it before doing these simplifications.

For the case when both LHS and RHS are bswaps I've allowed it to be moved if either LHS or RHS has a single use since that at least allows us to move it later where it might find another bswap to combine with and it decreases the use count on the other side so maybe the other user can be optimized.

Differential Revision: https://reviews.llvm.org/D34974

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307273 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 16:24:21 +00:00
Craig Topper
eebcffd281 [InstCombine] Don't create extra ConstantInt objects in foldSelectICmpAnd. NFCI
Instead just use APInt objects and only create a ConstantInt at the end if we need it for the Offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307270 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 15:58:54 +00:00
Wei Mi
4bbbd1a54e [LSR] Narrow search space by filtering non-optimal formulae with the same ScaledReg and Scale.
When the formulae search space is huge, LSR uses a series of heuristic to keep
pruning the search space until the number of possible solutions are within
certain limit.

The big hammer of the series of heuristics is NarrowSearchSpaceByPickingWinnerRegs,
which picks the register which is used by the most LSRUses and deletes the other
formulae which don't use the register. This is a effective way to prune the search
space, but quite often not a good way to keep the best solution. We saw cases before
that the heuristic pruned the best formula candidate out of search space.

To relieve the problem, we introduce a new heuristic called
NarrowSearchSpaceByFilterFormulaWithSameScaledReg. The basic idea is in order to
reduce the search space while keeping the best formula, we want to keep as many
formulae with different Scale and ScaledReg as possible. That is because the central
idea of LSR is to choose a group of loop induction variables and use those induction
variables to represent LSRUses. An induction variable candidate is often represented
by the Scale and ScaledReg in a formula. If we have more formulae with different
ScaledReg and Scale to choose, we have better opportunity to find the best solution.
That is why we believe pruning search space by only keeping the best formula with the
same Scale and ScaledReg should be more effective than PickingWinnerReg. And we use
two criteria to choose the best formula with the same Scale and ScaledReg. The first
criteria is to select the formula using less non shared registers, and the second
criteria is to select the formula with less cost got from RateFormula. The patch
implements the heuristic before NarrowSearchSpaceByPickingWinnerRegs, which is the
last resort.

Testing shows we get 1.8% and 2% on two internal benchmarks on x86. llvm nightly
testsuite performance is neutral. We also tried lsr-exp-narrow and it didn't help
on the two improved internal cases we saw.

Differential Revision: https://reviews.llvm.org/D34583


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307269 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 15:52:14 +00:00
Simon Pilgrim
54f05c4a85 [X86][SSE4A] Add support for shuffle combining to INSERTQI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307268 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 15:34:17 +00:00
Joel Jones
24fbea1d3b Doxygen formatting. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307263 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 14:17:36 +00:00
Mikael Holmen
0bce6b7bb4 [MachineVerifier] Add check that tied physregs aren't different.
Summary: Added MachineVerifier code to check register ties more thoroughly, especially so that physical registers that are tied are the same. This may help e.g. when creating MIR files.

Original patch by Jesper Antonsson

Reviewers: stoklund, sanjoy, qcolombet

Reviewed By: qcolombet

Subscribers: qcolombet, llvm-commits

Differential Revision: https://reviews.llvm.org/D34394

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307259 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 13:18:21 +00:00
Simon Pilgrim
2512875800 [X86][SSE] combineX86ShuffleChain - merge duplicate creations of integer mask types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307257 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 13:09:19 +00:00
Simon Pilgrim
479b8b3851 [X86][SSE] combineX86ShuffleChain - merge duplicate 'Zeroable' element masks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307255 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 12:40:10 +00:00
Simon Pilgrim
28b742e108 [X86][SSE4A] Add support for shuffle combining to EXTRQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307254 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 12:22:58 +00:00
Simon Pilgrim
8b3842edf5 [X86][SSE4A] Split EXTRQ/INSERTQ shuffle matching from lowering. NFCI.
First step toward supporting shuffle combining to EXTRQ/INSERTQ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307250 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 11:06:54 +00:00
Max Kazantsev
c539005888 Revert "Revert "Revert "[IndVars] Canonicalize comparisons between non-negative values and indvars"""
It appears that the problem is still there. Needs more analysis to understand why
SaturatedMultiply test fails.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307249 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 10:47:13 +00:00
David Stuttard
3b312dd635 [RegisterCoalescer] Fix for SubRange join unreachable
Summary:
During remat, some subranges might end up having invalid segments which caused problems for later
coalescing.

Added in a check to remove segments that are invalidated as part of the remat.

See http://llvm.org/PR33524

Subscribers: MatzeB, qcolombet

Differential Revision: https://reviews.llvm.org/D34391

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307247 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 10:07:57 +00:00
Diana Picus
b72872894c [ARM] GlobalISel: Map s32 G_FCMP in reg bank select
Map hard G_FCMP operands to FPR and the result to GPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307245 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 09:57:46 +00:00
Max Kazantsev
731b43312c Revert "Revert "[IndVars] Canonicalize comparisons between non-negative values and indvars""
It seems that the patch was reverted by mistake. Clang testing showed failure of the
MathExtras.SaturatingMultiply test, however I was unable to reproduce the issue on the
fresh code base and was able to confirm that the transformation introduced by the change
does not happen in the said test. This gives a strong confidence that the actual reason of
the failure of the initial patch was somewhere else, and that problem now seems to be
fixed. Re-submitting the change to confirm that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307244 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 09:57:41 +00:00
Diana Picus
e9e0d4fb83 [ARM] GlobalISel: Legalize G_FCMP for s32
This covers both hard and soft float.

Hard float is easy, since it's just Legal.

Soft float is more involved, because there are several different ways to
handle it based on the predicate: one and ueq need not only one, but two
libcalls to get a result. Furthermore, we have large differences between
the values returned by the AEABI and GNU functions.

AEABI functions return a nice 1 or 0 representing true and respectively
false. GNU functions generally return a value that needs to be compared
against 0 (e.g. for ogt, the value returned by the libcall is > 0 for
true).  We could introduce redundant comparisons for AEABI as well, but
they don't seem easy to remove afterwards, so we do different processing
based on whether or not the result really needs to be compared against
something (and just truncate if it doesn't).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307243 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 09:09:33 +00:00
Diana Picus
38c3b330a4 [ARM] GlobalISel: Widen s1, s8, s16 G_CONSTANT
Get the legalizer to widen small constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307239 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 08:04:16 +00:00
Frederich Munch
e533e91208 Avoid constructing GlobalExtensions only to find out it is empty.
Summary:
GlobalExtensions is dereferenced twice, once for iteration and then a check if it is empty.
As a ManagedStatic this dereference forces it's construction which is unnecessary.

Reviewers: efriedma, davide, mehdi_amini

Reviewed By: mehdi_amini

Subscribers: chapuni, llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D33381

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307229 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-06 00:09:09 +00:00
Eric Beckmann
b9f4c5114f Revert "Revert "Revert "Switch external cvtres.exe for llvm's own resource library."""
This reverts commit ae21ee0b6cacbc1efaf4d42502e71da2f0eb45c3.

The initial revert was done in order to prevent ongoing errors on
chromium bots such as CrWinClangLLD.  However, this was done haphazardly
and I didn't realize there were test and compilation failures, so this
revert was reverted.  Now that those have been fixed, we can revert the
revert of the revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307227 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 23:46:06 +00:00
Eric Beckmann
4f70e7e8d8 Revert "Revert "Revert "Replace trivial use of external rc.exe by writing our own .res file."""
This reverts commit 5fecbbbe5049665d86834cf69d8f75db4f392308.

The initial revert was done in order to prevent ongoing errors on
chromium bots such as CrWinClangLLD.  However, this was done haphazardly
and I didn't realize there were test and compilation failures, so this
revert was reverted.  Now that those have been fixed, we can revert the
revert of the revert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307226 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 23:45:50 +00:00
Craig Topper
3208bb2d1d [IR] Use CmpInst::isFPPredicate/isIntPredicate in a few other places. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307224 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 23:35:46 +00:00
Davide Italiano
1e0b73ce8b [GlobalOpt] Remove unreachable blocks before optimizing a function.
LLVM's definition of dominance allows instructions that are cyclic
in unreachable blocks, e.g.:

  %pat = select i1 %condition, @global, i16* %pat

because any instruction dominates an instruction in a block that's
not reachable from entry.
So, remove unreachable blocks from the function, because a) there's
no point in analyzing them and b) GlobalOpt should otherwise grow
some more complicated logic to break these cycles.

Differential Revision:  https://reviews.llvm.org/D35028

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307215 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 22:28:28 +00:00
Vadim Chugunov
a671f7f9d2 Fix libcall expansion creating DAG nodes with invalid type post type legalization.
If we are lowering a libcall after legalization, we'll split the return type into a pair of legal values.

Patch by Jatin Bhateja and Eli Friedman.

Differential Revision: https://reviews.llvm.org/D34240



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307207 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 22:01:49 +00:00
Brendon Cahoon
f2a1839566 [DependenceAnalysis] Make sure base objects are the same when comparing GEPs
The dependence analysis was returning incorrect information when using the GEPs
to compute dependences. The analysis uses the GEP indices under certain
conditions, but was doing it incorrectly when the base objects of the GEP are
aliases, but pointing to different locations in the same array.

This patch adds another check for the base objects. If the base pointer SCEVs
are not equal, then the dependence analysis should fall back on the path
that uses the whole SCEV for the dependence check. This fixes PR33567.

Differential Revision: https://reviews.llvm.org/D34702


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307203 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 21:35:47 +00:00
Craig Topper
3af013231e [InstCombine] Use CmpInst::Predicate with m_Cmp instead of ICmpInst::Predicate. NFC
There isn't really an ICmpInst version so we're just accessing the CmpInst version through inheritance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307199 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 20:31:00 +00:00
Sam Clegg
640fb6d894 [WebAssembly] Fix types for address taken functions
Differential Revision: https://reviews.llvm.org/D34966

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307198 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 20:25:08 +00:00
Sam Clegg
a6a29d93c8 [WebAssembly] MC: Don't generate extra types for weak alias
Previously we were generating a void(void) function type
for a weak alias.  Update the weak-alias test case to
catch this.

Differential Revision: https://reviews.llvm.org/D34734

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307194 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 20:09:26 +00:00
Eric Beckmann
045760e434 Revert "Revert "Replace trivial use of external rc.exe by writing our own .res file.""
This reverts commit 8c8dce3b8f15d6ebaefc35ce88f15a85c8cdbd6e.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307191 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 19:04:48 +00:00
Eric Beckmann
1efceea97e Revert "Revert "Switch external cvtres.exe for llvm's own resource library.""
This reverts commit 165e578e47f1cd38191120aad23a9020fb5476dd.

Forgot to run tests on this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307190 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 19:04:33 +00:00
Eric Beckmann
9b6f55389e Revert "Switch external cvtres.exe for llvm's own resource library."
This reverts commit 600d52c278e123dd08bee24c1f00932b55add8de.

This patch still seems to break CrWinClangLLD, reverting until I can
find root problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307189 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 18:59:16 +00:00
Eric Beckmann
7cacca2b9b Revert "Replace trivial use of external rc.exe by writing our own .res file."
This patch still seems to break CrWinClangLLD, reverting this once more
until I can discover root problem.

This reverts commit 3dbbc8ce43be50ffde2b1c655c6d3a25796fe78b.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307188 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 18:59:01 +00:00
Quentin Colombet
d268a8d71a [AMDGPU] Move GISel accessor initialization from TargetMachine to Subtarget.
NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307186 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 18:40:56 +00:00
Sean Fertile
4ddfd12ff6 [Power9] Disable removing extra swaps on P9.
On power 8 we sometimes insert swaps to deal with the difference between
Little-Endian and Big-Endian. The swap removal pass is supposed to clean up
these swaps. On power 9 we don't need this pass since we do not need to insert
the swaps in the first place.

Commiting on behalf of Stefan Pintilie.
Differential Revision: https://reviews.llvm.org/D34627

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307185 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 18:37:10 +00:00
Simon Pilgrim
5a32446d7b {DAGCombiner] Fold (rot x, 0) -> x
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307184 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 18:27:11 +00:00
Sean Fertile
cb358c5493 [PowerPC] Make sure that we remove dead PHI nodes after the PPCCTRLoops pass.
Commiting on behalf of Stefan Pintilie.
Differential Revision: https://reviews.llvm.org/D34829

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307180 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 17:57:57 +00:00
Andrew Zhogin
e54a2b399d [DAGCombiner] visitRotate patch to optimize pair of ROTR/ROTL instructions into one with combined shift operand.
For two ROTR operations with shifts C1, C2; combined shift operand will be (C1 + C2) % bitsize.

Differential revision: https://reviews.llvm.org/D12833


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307179 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 17:55:42 +00:00
Tony Jiang
d1071cff22 [Power9] Exploit vector extract with variable index.
This patch adds the exploitation for new power 9 instructions which extract
variable elements from vectors:
VEXTUBLX
VEXTUBRX
VEXTUHLX
VEXTUHRX
VEXTUWLX
VEXTUWRX

Differential Revision: https://reviews.llvm.org/D34032
Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307174 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 16:55:00 +00:00
Tony Jiang
ee1d801b4f [Power9] Exploit vector integer extend instructions when indices aren't correct.
This patch adds on to the exploitation added by https://reviews.llvm.org/D33510.
This now catches build vector nodes where the inputs are coming from sign
extended vector extract elements where the indices used by the vector extract
are not correct. We can still use the new hardware instructions by adding a
shuffle to move the elements to the correct indices. I introduced a new PPCISD
node here because adding a vector_shuffle and changing the elements of the
vector_extracts was getting undone by another DAG combine.

Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com)
Differential Revision: https://reviews.llvm.org/D34009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307169 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 16:00:38 +00:00
David Blaikie
4a35644b43 DebugInfo: Generalize LoadedObjectInfoHelper from RuntimeDyld
Make it usable by any class derived (even indirectly) from
LoadedObjectInfo by allowing a custom base class to be specified and
perfect forwarding to the ctor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307166 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 15:23:56 +00:00
Daniel Sanders
b26b47eeb0 [globalisel][tablegen] Finish fixing compile-time regressions by merging the matcher and emitter state machines.
Summary:
Also, made a few minor tweaks to shave off a little more cumulative memory consumption:
* All rules share a single NewMIs instead of constructing their own. Only one
  will end up using it.
* Use MIs.resize(1) instead of MIs.clear();MIs.push_back(I) and prevent
  GIM_RecordInsn from changing MIs[0].

Depends on D33764

Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar

Reviewed By: ab

Subscribers: kristof.beyls, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D33766

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307159 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 14:50:18 +00:00
Dinar Temirbulatov
18b9e001a8 [SLPVectorizer] Add an extra parameter to cancelScheduling function, NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307158 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 13:53:03 +00:00
David Green
a33c5722b0 [IndVarSimplify] Add AShr exact flags using induction variables ranges.
This adds exact flags to AShr/LShr flags where we can statically
prove it is valid using the range of induction variables. This
allows further optimisations to remove extra loads.

Differential Revision: https://reviews.llvm.org/D34207



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307157 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 13:25:58 +00:00
Ulrich Weigand
4c8480dbc5 [SystemZ] Simplify handling of 128-bit multiply/divide instruction
Several integer multiply/divide instructions require use of a
register pair as input and output.  This patch moves setting
up the input register pair from C++ code to TableGen, simplifying
the whole process and making it more easily extensible.

No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307155 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 13:17:31 +00:00
Ulrich Weigand
55e17e75fd [SystemZ] Small cleanups to SystemZScheduleZ13.td
Fixes a couple of whitespace errors, re-sorts the vector floating-point
instructions to make them more easily extensible, and adds a missing
pseudo instruction.

No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307154 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 13:14:43 +00:00
Diana Picus
f1715a330a [GlobalISel] Refactor Legalizer helpers for libcalls
We used to have a helper that replaced an instruction with a libcall.
That turns out to be too aggressive, since sometimes we need to replace
the instruction with at least two libcalls. Therefore, change our
existing helper to only create the libcall and leave the instruction
removal as a separate step. Also rename the helper accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307149 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 12:57:24 +00:00
Sjoerd Meijer
8b755a3a21 [AsmParser] Mnemonic Spell Corrector
This implements suggesting other mnemonics when an invalid one is specified,
for example:

$ echo "adXd r1,r2,#3" | llvm-mc -triple arm
<stdin>:1:1: error: invalid instruction, did you mean: add, qadd?
adXd r1,r2,#3
^

The implementation is target agnostic, but as a first step I have added it only
to the ARM backend; so the ARM backend is a good example if someone wants to
enable this too for another target.

Differential Revision: https://reviews.llvm.org/D33128


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307148 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 12:39:13 +00:00
Diana Picus
501e5159ca [ARM] GlobalISel: Extract tiny helper. NFC
Extract functionality for determining if the target uses AEABI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307145 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 11:53:51 +00:00
Diana Picus
5d663de6b1 [MachineIRBuilder] Fix formatting. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307144 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 11:47:23 +00:00