35615 Commits

Author SHA1 Message Date
Tim Northover
5a4800a05f ARM: override cost function to re-enable ConstantHoisting (& fix it).
At some point, ARM stopped getting any benefit from ConstantHoisting because
the pass called a different variant of getIntImmCost. Reimplementing the
correct variant revealed some problems, however:

  + ConstantHoisting was modifying switch statements. This is simply invalid,
    the cases must remain integer constants no matter the notional cost.
  + ConstantHoisting was mangling alloca instructions in the entry block. These
    should be handled by FrameLowering, so constants actually have a cost of 0.
    Worse, the resulting bitcasts meant they became dynamic allocas.

rdar://25707382

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266260 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 23:08:27 +00:00
Matthias Braun
3df4c84057 ARM: Use a callee save register for the swiftself parameter.
It is very likely that the swiftself parameter is alive throughout most
functions function so putting it into a callee save register should
avoid spills for the callers with only a minimum amount of extra spills
in the callees.

Currently the generated code is correct but unnecessarily spills and
reloads arguments passed in callee save registers, I will address this
in upcoming patches.

This also adds a missing check that for tail calls the preserved value
of the caller must be the same as the callees parameter.

Differential Revision: http://reviews.llvm.org/D18901

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266253 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 21:43:25 +00:00
Matthias Braun
cd45ee92d7 X86: Use a callee save register for the swiftself parameter.
It is very likely that the swiftself parameter is alive throughout most
functions function so putting it into a callee save register should
avoid spills for the callers with only a minimum amount of extra spills
in the callees.

Currently the generated code is correct but unnecessarily spills and
reloads arguments passed in callee save registers, I will address this
in upcoming patches.

This also adds a missing check that for tail calls the preserved value
of the caller must be the same as the callees parameter.

Differential Revision: http://reviews.llvm.org/D18902

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266252 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 21:43:21 +00:00
Matthias Braun
9f620df2ef AArch64: Use a callee save registers for swiftself parameters
It is very likely that the swiftself parameter is alive throughout most
functions function so putting it into a callee save register should
avoid spills for the callers with only a minimum amount of extra spills
in the callees.

Currently the generated code is correct but unnecessarily spills and
reloads arguments passed in callee save registers, I will address this
in upcoming patches.

This also adds a missing check that for tail calls the preserved value
of the caller must be the same as the callees parameter.

Differential Revision: http://reviews.llvm.org/D19007

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266251 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 21:43:16 +00:00
Kevin Enderby
63247519d7 Start to add real error messages for malformed Mach-O files.
And update the existing test cases in test/Object/macho-invalid.test
to use llvm-objdump with the -macho option to produce these
error messages and stop producing the generic "Invalid data
was encountered while parsing the file" message.

Working from the beginning of the file, if the mach header is too large for
the size of the file and then if the load commands that follow extend past
the end of the file these two errors now generate correct error messages.

Both of these have existing test cases in test/Object/macho-invalid.test .

But the first with macho-invalid-header it will never trigger the error message
"mach header extends past the end of the file" using any of the llvm tools as
they all use identify_magic() which rejects files with the correct magic number
that are too small in size.  So I tested this by hacking that code and seeing the
error message down in parseHeader() really does happen.  So in case there
is ever code in llvm that directly calls createMachOObjectFile() this error
message will be correctly produced.

The second error message of "load commands extends past the end of the file"
is triggered by a number of existing tests cases in test/Object/macho-invalid.test .
Also other tests trigger different error messages now like "ilocalsym plus
nlocalsym in LC_DYSYMTAB load command extends past the end of the
symbol table".

There are two existing test cases that still get the "Invalid data was encountered ..."
error messages that I will tackle next.  But they will involve a bit of pluming an
Expect<...> up through the call stack and I want to do those as separate changes.

FYI, for those test cases that were trying to test specific errors that now get
different errors I’ll fix those in follow on changes and create new test cases
for those so they test the error they were meant to test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266248 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 21:17:58 +00:00
Sanjay Patel
f301f27d4e [x86] add tests to show potential BMI optimization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266243 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 20:40:43 +00:00
Tim Northover
6d56779f41 AsmParser: record "# line file" context to calculate location for diag
Since we can't emit diagnostics for missing "jmp 1f" labels until the end of
the file, we need to be able to restore the context used to calculate
file/line. This is basically the "# line file" directive that's being used at
the time the expression is seen.

rdar://25706972

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266238 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 19:46:54 +00:00
Easwaran Raman
f001eb54c5 Test case for r265852.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266237 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 19:43:31 +00:00
Peter Collingbourne
9e81c60d6e LibDriver: Silently do nothing when provided no inputs.
This behavior is strange, but it matches lib.exe. Based on a patch by
Nico Weber.

Fixes PR27335.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266236 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 19:36:04 +00:00
Betul Buyukkurt
5a486ec618 [PGO] Remove redundant VP instrumentation
LLVM optimization passes may reduce a profiled target expression
to a constant. Removing runtime calls at such instrumentation points
would help speedup the runtime of the instrumented program.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266229 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 18:52:19 +00:00
Nemanja Ivanovic
b935913676 [PowerPC] Basic support for P9 byte comparison and count trailing zero insns
This patch corresponds to review:
http://reviews.llvm.org/D17850

This patch implements the following instructions:
cmprb, cmpeqb, cnttzw, cnttzw., cnttzd, cnttzd.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266228 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 18:51:18 +00:00
Evandro Menezes
891346a0b1 [AArch64] Disable LDP/STP for quads
Disable LDP/STP for quads on Exynos M1 as they are not as efficient as pairs
of regular LDR/STR.

Patch by Abderrazek Zaafrani <a.zaafrani@samsung.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266223 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 18:31:45 +00:00
Davide Italiano
4a1c79f1f4 Revert "[IR/Verifier] Each DISubprogram with isDefinition: true must belong to a CU."
This reverts commit r266102. The O(N^2) verifier check causes timeouts
in LTO test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266221 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 18:08:07 +00:00
Nirav Dave
100a6beac6 Cleanup Store Merging in UseAA case
This patch fixes a bug (PR26827) when using anti-aliasing in store
merging. This sets the chain users of the component stores to point to
the new store instead of the component stores chain parent.

Reviewers: jyknight

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18909

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266217 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 17:27:26 +00:00
Mehdi Amini
387bdb41b0 Revert "Make aliases explicit in the summary"
Inadvertently commited...

This reverts commit e618ec93786d99df2ddf280ad2d5e02f5516cecf.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266215 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 17:20:07 +00:00
Mehdi Amini
e618ec9378 Make aliases explicit in the summary
Summary:
To be able to work accurately on the reference graph when taking decision
about internalizing, promoting, renaming, etc. We need to have the alias
information explicit.

Reviewers: tejohnson

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18836

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266214 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 17:18:42 +00:00
Tim Northover
31cadd791a AArch64: don't create instructions that write to xzr/wzr twice.
These are unpredictable even on AArch64.

Patch by Yichao Yu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266206 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 16:25:39 +00:00
Artem Tamazov
075abcbd06 [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status
Tests added along with implemented feature.
Note that there is a small leftover of unecessary MI sheduling issue
(more info in the review). CodeGen/AMDGPU/salu-to-valu.ll updated to fix
the false regression.

TODO: Support for TTMP quads, comma-separated syntax in "[]" and more.

Differential Revision: http://reviews.llvm.org/D17825

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266205 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 16:18:41 +00:00
Zoran Jovanovic
d61f2a5190 [mips] Fix emitAtomicCmpSwapPartword to handle 64 bit pointers correctly
Differential Revision: http://reviews.llvm.org/D18995


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266204 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 16:02:25 +00:00
Vasileios Kalintiris
21bbc49406 [mips] Sign-extend i32 values truncated from previously zero-extended i32 values.
Summary:
This is a special case for MIPS64 because the architecture requires
properly 32-bit sign-extended values in the register containers.

Additionaly, we merge consecutive trunc + AssertZExt nodes in order
to avoid unnecessary sign-extensions when the extension comes from a
type smaller than i32.

Reviewers: dsanders

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D18893

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266203 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 15:07:45 +00:00
David L Kreitzer
3592381ea1 Simplify strlen to a subtraction for certain cases.
Patch by Li Huang (li1.huang@intel.com)

Differential Revision: http://reviews.llvm.org/D18230


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266200 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 14:31:06 +00:00
Simon Pilgrim
11615f462c [X86][SSE] Regenerated vector integer absolute tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266194 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 12:40:22 +00:00
Petar Jovanovic
396d592ab0 Calculate __builtin_object_size when pointer depends on a condition
This patch fixes calculating of builtin_object_size if it depends on a
condition. Before this patch compiler did not know how to calculate the
object size when it finds a condition that cannot be eliminated.
This patch enables calculating of builtin_object_size even in case when
condition cannot be eliminated by choosing minimum or maximum value as a
result from condition. Choosing minimum or maximum value from condition
is based on the second argument of __builtin_object_size function.

Patch by Strahinja Petrovic.

Differential Revision: http://reviews.llvm.org/D18438


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266193 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 12:25:25 +00:00
Simon Pilgrim
56547528a2 Added missing autogeneration note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266185 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 09:28:44 +00:00
Zlatko Buljan
2cc36cb95b [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions
Differential Revision: http://reviews.llvm.org/D17137

This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068.
There was the problem with test-suite failure.
The problem is hopefully solved with dependant patch so this patch is commited again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266179 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 08:02:26 +00:00
David Majnemer
1559762512 [InstCombine] We folded an fcmp to an i1 instead of a vector of i1
Remove an ad-hoc transform in InstCombine and replace it with more
general machinery (ValueTracking, InstructionSimplify and VectorUtils).

This fixes PR27332.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266175 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 06:55:52 +00:00
Hrvoje Varga
fd6b04ca1d [mips][microMIPS] Fix for "Cannot copy registers" assertion
Differential Revision: http://reviews.llvm.org/D17068

This changes contains fix for failing test-suite. So, this patch should hopefully work now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266171 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 06:17:21 +00:00
Mehdi Amini
8fbafc9f4e Refactor the InternalizePass into a helper class, and expose it through a public free function (NFC)
There is really no reason to require to instanciate a pass manager to
internalize.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266167 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 05:25:08 +00:00
Wei Mi
815b02e9ce Recommit r265547, and r265610,r265639,r265657 on top of it, plus
two fixes with one about error verify-regalloc reported, and
another about live range update of phi after rematerialization.

r265547:
Replace analyzeSiblingValues with new algorithm to fix its compile
time issue. The patch is to solve PR17409 and its duplicates.

analyzeSiblingValues is a N x N complexity algorithm where N is
the number of siblings generated by reg splitting. Although it
causes siginificant compile time issue when N is large, it is also
important for performance since it removes redundent spills and
enables rematerialization.

To solve the compile time issue, the patch removes analyzeSiblingValues
and replaces it with lower cost alternatives containing two parts. The
first part creates a new spill hoisting method in postOptimization of
register allocation. It does spill hoisting at once after all the spills
are generated instead of inside every instance of selectOrSplit. The
second part queries the define expr of the original register for
rematerializaiton and keep it always available during register allocation
even if it is already dead. It deletes those dead instructions only in
postOptimization. With the two parts in the patch, it can remove
analyzeSiblingValues without sacrificing performance.

Patches on top of r265547:
r265610 "Fix the compare-clang diff error introduced by r265547."
r265639 "Fix the sanitizer bootstrap error in r265547."
r265657 "InlineSpiller.cpp: Escap \@ in r265547. [-Wdocumentation]"

Differential Revision: http://reviews.llvm.org/D15302
Differential Revision: http://reviews.llvm.org/D18934
Differential Revision: http://reviews.llvm.org/D18935
Differential Revision: http://reviews.llvm.org/D18936


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266162 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 03:08:27 +00:00
Matt Arsenault
f294b0931f AMDGPU: Add test for m0 initialization in basic loop
Initialization of m0 is emitted for each LDS operation, so
every block with LDS usage ends up with one. MachineLICM
used to fail to hoist this out of the loop, so every loop
iteration with LDS usage in it would re-initialize it.

This seems to be fixed now, so add a test to make sure that
it stays this way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266156 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 00:39:52 +00:00
Matt Arsenault
d5a8ffbb92 AMDGPU: Remove leftover ShaderType attributes in tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266155 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 00:39:48 +00:00
Justin Bogner
ae7cc5f233 CodeGen: Clear the MFI's save and restore point after PrologEpilogInserter
This state is no longer useful and not guaranteed to be valid in later
codegen passes. For example, see the added test, which would print a
savepoint of %bb.-1 without this change, and crashes with a
use-after-free error under ASan if you apply the recycling allocator
patch from llvm.org/PR26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266150 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 23:21:53 +00:00
Sanjay Patel
9078f559b2 [x86, InstCombine] fix masked load pass-through operand to be a zero vector
This bug was introduced with:
http://reviews.llvm.org/rL262269

AVX masked loads are specified to set vector lanes to zero when the high bit of the mask
element for that lane is zero:
"If the mask is 0, the corresponding data element is set to zero in the load form of these
instructions, and unmodified in the store form." --Intel manual

Differential Revision: http://reviews.llvm.org/D19017



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266148 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 23:16:23 +00:00
Davide Italiano
e6f98f0821 [DebugInfo] Add error message to test.
Suggested by Rafael as post-commit review (r266102).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266134 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 21:44:16 +00:00
Mehdi Amini
28b33112e2 Add a pass to name anonymous/nameless function
Summary:
For correct handling of alias to nameless
function, we need to be able to refer them through a GUID in the summary.
Here we name them using a hash of the non-private global names in the module.

Reviewers: tejohnson

Subscribers: joker.eph, llvm-commits

Differential Revision: http://reviews.llvm.org/D18883

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266132 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 21:35:28 +00:00
Mehdi Amini
e58bfc97e6 Move summary creation out of llvm-as into opt
Summary:
Let keep llvm-as "dumb": it converts textual IR to bitcode. This
commit removes the dependency from llvm-as to libLLVMAnalysis.
We'll add back summary in llvm-as if we get to a textual
representation for it at some point. In the meantime, opt seems
like a better place for that.

Reviewers: tejohnson

Subscribers: joker.eph, llvm-commits

Differential Revision: http://reviews.llvm.org/D19032

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266131 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 21:35:18 +00:00
Nicolai Haehnle
756309c45b AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics
Summary:
They correspond to BUFFER_LOAD/STORE_DWORD[_X2,X3,X4] and mostly behave like
llvm.amdgcn.buffer.load/store.format. They will be used by Mesa for SSBO and
atomic counters at least when robust buffer access behavior is desired.
(These instructions perform no format conversion and do buffer range checking
per component.)

As a side effect of sharing patterns with llvm.amdgcn.buffer.store.format,
it has become trivial to add support for the f32 and v2f32 variants of that
intrinsic, so the patch does so.

Also DAG-ify (and fix) some tests that I noticed intermittent failures in
while developing this patch.

Some tests were (temporarily) adjusted for the required mayLoad/hasSideEffects
changes to the BUFFER_STORE_DWORD* instructions. See also
http://reviews.llvm.org/D18291.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18292

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266126 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 21:18:10 +00:00
James Y Knight
238d8199af Add __atomic_* lowering to AtomicExpandPass.
(Recommit of r266002, with r266011, r266016, and not accidentally
including an extra unused/uninitialized element in LibcallRoutineNames)

AtomicExpandPass can now lower atomic load, atomic store, atomicrmw, and
cmpxchg instructions to __atomic_* library calls, when the target
doesn't support atomics of a given size.

This is the first step towards moving all atomic lowering from clang
into llvm. When all is done, the behavior of __sync_* builtins,
__atomic_* builtins, and C11 atomics will be unified.

Previously LLVM would pass everything through to the ISelLowering
code. There, unsupported atomic instructions would turn into __sync_*
library calls. Because of that behavior, Clang currently avoids emitting
llvm IR atomic instructions when this would happen, and emits __atomic_*
library functions itself, in the frontend.

This change makes LLVM able to emit __atomic_* libcalls, and thus will
eventually allow clang to depend on LLVM to do the right thing.

It is advantageous to do the new lowering to atomic libcalls in
AtomicExpandPass, before ISel time, because it's important that all
atomic operations for a given size either lower to __atomic_*
libcalls (which may use locks), or native instructions which won't. No
mixing and matching.

At the moment, this code is enabled only for SPARC, as a
demonstration. The next commit will expand support to all of the other
targets.

Differential Revision: http://reviews.llvm.org/D18200

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266115 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 20:18:48 +00:00
Derek Schuff
83c1c10eb3 [WebAssembly] Fix debug info in reg-stackify.ll test
It lacked a CU and thus became invalid with r266102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266114 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 20:12:05 +00:00
Tom Stellard
cb6c943dc2 AMDGPU/SI: Insert wait states required after v_readfirstlane on SI
Summary:
We will be able to handle this case much better once the hazard recognizer
is finished, but this conservative implementation  fixes a hang with the piglit
test:

spec/arb_arrays_of_arrays/execution/sampler/fs-nested-struct-arrays-nonconst-nested-arra

Reviewers: arsenm, nhaehnle

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18988

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266105 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 18:40:43 +00:00
Matt Arsenault
87f61332d1 AMDGPU: Eliminate half of i64 or if one operand is zero_extend from i32
This helps clean up some of the mess when expanding unaligned 64-bit
loads when changed to be promote to v2i32, and fixes situations
where or x, 0 was emitted after splitting 64-bit ors during moveToVALU.

I think this could be a generic combine but I'm not sure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266104 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 18:24:38 +00:00
Davide Italiano
361311da1f [IR/Verifier] Each DISubprogram with isDefinition: true must belong to a CU.
Add a check to catch violations. ~60 tests were broken and prevented
this change to be committed. Adrian and I (thanks Adrian!) went
through them in the last week or so updating. The check can be
done more efficiently but I'd still like to get this in ASAP to
avoid more broken tests to be checked in (if any).

PR:  27101

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266102 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 18:22:33 +00:00
Nicolai Haehnle
4bd7005237 AMDGPU/SI: Fix a mis-compilation of multi-level breaks
Summary:
Under certain circumstances, multi-level breaks (or what is understood by
the control flow passes as such) could be miscompiled in a way that causes
infinite loops, by emitting incorrect control flow intrinsics.

This fixes a hang in
dEQP-GLES3.functional.shaders.loops.while_dynamic_iterations.conditional_continue_vertex

Reviewers: arsenm, tstellarAMD

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266088 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 16:10:38 +00:00
Artur Pilipenko
80ce67004b Support arbitrary addrspace pointers in masked load/store intrinsics
This is a resubmittion of 263158 change.

This patch fixes the problem which occurs when loop-vectorize tries to use @llvm.masked.load/store intrinsic for a non-default addrspace pointer. It fails with "Calling a function with a bad signature!" assertion in CallInst constructor because it tries to pass a non-default addrspace pointer to the pointer argument which has default addrspace.

The fix is to add pointer type as another overloaded type to @llvm.masked.load/store intrinsics.

Reviewed By: reames

Differential Revision: http://reviews.llvm.org/D17270


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266086 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 15:58:04 +00:00
Davide Italiano
fc57f09333 [Bitcode] Fix + regenerate old test so that it includes a DICompileUnit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266085 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 15:51:23 +00:00
Geoff Berry
3c28f60569 [ScheduleDAGInstrs] Handle instructions with multiple MMOs
Summary:
In getUnderlyingObjectsForInstr(): Don't give up on instructions with
multiple MMOs, instead look through all the MMOs and if they all meet
the conservative criteria previously used for single MMO instructions,
then return all of the underlying objects derived from the MMOs.

The change to ScheduleDAGInstrs::buildSchedGraph() is needed to avoid
the case where multiple underlying objects are present and are related
in such a way that successive iterations of the loop end up adding a
dependency from an instruction to itself.

Reviewers: atrick, hfinkel

Subscribers: MatzeB, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D18093

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266084 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 15:50:19 +00:00
Than McIntosh
a58cdd3483 Test commit, NFC.
Adds a blank line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266082 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 15:35:05 +00:00
Petar Jovanovic
7655423622 [mips] add assembler support for .set arch=octeon
This patch enables assembler support for .set arch=octeon.
It will fix issues with inline assembler when this directive is used.

Patch by Strahinja Petrovic.

Differential Revision: http://reviews.llvm.org/D18548


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266081 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 15:28:16 +00:00
Aaron Ballman
e3315093af Moving llvm-test-depends and test-depends into the Tests folder; NFC, this simply cleans up the generated solution so that these targets don't live in the root folder of the IDE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266078 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 15:09:14 +00:00
Matt Arsenault
d8f221e6c0 AMDGPU: Implement i64 global atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266075 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-12 14:05:11 +00:00