5 Commits

Author SHA1 Message Date
Simon Pilgrim
5d31f856ab [X86][AVX512] Add support for v2i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets
Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287882 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-24 14:46:55 +00:00
Simon Pilgrim
e547b01b86 [X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets
Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287762 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-23 14:01:18 +00:00
Simon Pilgrim
fca1eeaa1f [CostModel][X86] Add v2f32 -> v2i64 fptosi/fptoui cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287756 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-23 11:43:00 +00:00
Simon Pilgrim
e615ec6e15 [X86][SSE] Add lowering to cvttpd2dq/cvttps2dq for sitofp v2f64/2f32 to 2i32
As discussed on PR28461 we currently miss the chance to lower "fptosi <2 x double> %arg to <2 x i32>" to cvttpd2dq due to its use of illegal types.

This patch adds support for fptosi to 2i32 from both 2f64 and 2f32.

It also recognises that cvttpd2dq zeroes the upper 64-bits of the xmm result (similar to D23797) - we still don't do this for the cvttpd2dq/cvttps2dq intrinsics - this can be done in a future patch.

Differential Revision: https://reviews.llvm.org/D23808

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284459 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-18 07:42:15 +00:00
Simon Pilgrim
065e5924cd [CostModel][X86] Added tests for current fptosi/fptoui costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283047 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-01 19:09:59 +00:00