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4 Commits

Author SHA1 Message Date
Matt Arsenault
68f559ea61 AMDGPU: Fix ctlz combine for sub 32-bit types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257353 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-01-11 17:02:06 +00:00
Matt Arsenault
f12a12cd25 AMDGPU: Pattern match ffbh pattern to instruction. 
The hardware instruction's output on 0 is -1 rather than 32.
Eliminate a test and select to -1. This removes an extra instruction
from the compatability function with HSAIL's firstbit instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257352 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-01-11 17:02:00 +00:00
Matt Arsenault
01a6cb6ce3 AMDGPU: Custom lower i64 ctlz 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257348 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-01-11 16:50:29 +00:00
Matt Arsenault
3bbc287300 LegalizeDAG: Expand ctlz with ctlz_zero_undef if legal 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257345 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-01-11 16:37:46 +00:00