130675 Commits

Author SHA1 Message Date
Simon Dardis
ad461d6067 [mips] Fix select patterns for MIPS64
When targetting MIPS64R6 some of the patterns for select were guarded by a
broken predicate. The predicate was supposed to test if a constant value
could fit in a 16 bit zero-extended field. Instead the value was tested to
fit in a 16 bit sign-extended field. For negative constants of native word
width this resulted in wrong code generation.

Reviewers: vkalintiris, dsanders

Differential Review: http://reviews.llvm.org/D19378


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267151 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 13:19:22 +00:00
Teresa Johnson
47534d9ca6 Document source_filename in LangRef.
Summary: Add documentation for new LLVM IR source_filename identifier.

Reviewers: joker.eph, majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18857

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267150 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 13:09:17 +00:00
Vasileios Kalintiris
e86221b7cc [mips] Fix a small typo that would leave BLTZC out of getAnalyzableBrOpc().'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267149 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 13:05:51 +00:00
Daniel Sanders
cd2984fe3c Revert r267049, r26706[16789], r267071 - Refactor raw pdb dumper into library
r267049 broke multiple buildbots (e.g. clang-cmake-mips, and clang-x86_64-linux-selfhost-modules) which the follow-ups have not yet resolved and this is preventing subsequent committers from being notified about additional failures on the affected buildbots.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267148 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 12:04:42 +00:00
Nikolay Haustov
c42b2f3bd2 AMDGPU/SI: Add test missed in rL266865
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267144 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 11:39:43 +00:00
Silviu Baranga
883a09c5a6 [InstCombine] Preserve fast math flags when combining PHIs
Summary:
When optimizing PHIs which have inputs floating point binary
operators, we preserve all IR flags except the fast math
flags.

This change removes the logic which tracked some of the IR flags
(no wrap, exact) and replaces it by doing an and on the IR flags of
all inputs to the PHI - which will also handle the fast math
flags.

Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D19370

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267139 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 11:21:36 +00:00
Hrvoje Varga
fed867f0f8 [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions
Differential Revision: http://reviews.llvm.org/D19354


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267137 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 11:18:40 +00:00
Zoran Jovanovic
c1499f8232 [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocation
Differential Revision: http://reviews.llvm.org/D15026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267130 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 10:15:12 +00:00
Eric Liu
2321e6017b Fix -Wunused-variable in non-asserts build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267128 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 09:50:31 +00:00
Daniel Sanders
c4f4f71fb7 Revert r267098 - [MachineCombiner] Support for floating-point FMA on ARM64
It introduced buildbot failures on clang-cmake-mips, clang-ppc64le-linux, among others.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267127 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 09:37:26 +00:00
Ashutosh Nema
91d7ac06b6 [X86]: Changing cost for “TRUNCATE v16i32 to v16i8” in SSE4.1 mode.
Summary:
rL256194 transforms truncations between vectors of integers into PACKUS/PACKSS
operations during DAG combine. This generates better code for truncate, so cost
of truncate needs to be changed but looks like it got changed only in SSE2 table
Whereas this change is also applicable for SSE4.1, so the cost of truncate needs
to be changed for that as well. Cost of “TRUNCATE v16i32 to v16i8” & “TRUNCATE 
v16i16 to v16i8” should be same in SSE4.1 & SSE2 table. Removing their cost from
SSE4.1, so it will fall back to SSE2.

Reviewers: Simon Pilgrim


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267123 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 08:34:05 +00:00
Chris Dewhurst
4572b689c6 [Sparc] This provides support for itineraries on Sparc.
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.

The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.

As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.

Phabricator Review: http://reviews.llvm.org/D19359

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267121 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 08:17:17 +00:00
Chris Dewhurst
82da5a1b3d The following code would not work before this patch, due to the inability to take the address of a global object:
void func1() {

...
}

int main(int argc, char** argv) {

void (*pFunc)();
pFunc = &func1
pFunc();
...
}

Phabricator review: http://reviews.llvm.org/D19368

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267120 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 08:13:47 +00:00
Vedant Kumar
8866d94a61 Revert "Initial implementation of optimization bisect support."
This reverts commit r267022, due to an ASan failure:

  http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/1549

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267115 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 06:51:37 +00:00
Zlatko Buljan
6a025fe5e2 [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions
Differential Revision: http://reviews.llvm.org/D18687


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267114 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 06:44:34 +00:00
David Majnemer
582e856107 [GVN] Respect fast-math-flags on fcmps
We assumed that flags were only present on binary operators.  This is
not true, they may also be present on calls and fcmps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267113 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 06:37:51 +00:00
David Majnemer
fd026c3bc6 Fix some spelling mistakes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267112 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 06:37:48 +00:00
David Majnemer
91e5e85831 [EarlyCSE] Take the intersection of flags on instructions
EarlyCSE had inconsistent behavior with regards to flag'd instructions:
- In some cases, it would pessimize if the available instruction had
  different flags by not performing CSE.
- In other cases, it would miscompile if it replaced an instruction
  which had no flags with an instruction which has flags.

Fix this by being more consistent with our flag handling by utilizing
andIRFlags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267111 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 06:37:45 +00:00
Sanjoy Das
fdc9ad7da2 [SCEV] Extract out a isSCEVExprNeverPoison helper; NFCI
Summary:
Also adds a small comment blurb on control flow + no-wrap flags, since
that question came up a few days back on llvm-dev.

Reviewers: bjarke.roune, broune

Subscribers: sanjoy, mcrosier, llvm-commits, mzolotukhin

Differential Revision: http://reviews.llvm.org/D19209

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267110 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 05:38:54 +00:00
Craig Topper
da09533754 [SystemZ] Mark CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF as Expand instead of Custom since the custom logic just did what Expand does when CTTZ/CTLZ are Legal. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267109 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 05:29:58 +00:00
Craig Topper
f1102bae76 [Lanai] Set CTLZ_ZERO_UNDEF/CTTZ_ZERO_UNDEF to Expand instead of Legal so they will be converted to CTLZ/CTTZ by LegalizeDAG. Remove extra instructions that only existed to to contain patterns that match the zero_undef operations. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267108 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 05:13:01 +00:00
Craig Topper
b23f14f601 [Lanai] Remove unused methods declarations. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267107 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 05:12:57 +00:00
Mehdi Amini
4302c2c052 Clean the API for CollectAsmUndefinedRefs, taking a Triple and a String InlineAsm instead of a Module (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267106 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 04:58:12 +00:00
Mehdi Amini
bfce19c73c IRObjectFile, clang-format fixup for r267104
From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267105 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 04:49:46 +00:00
Mehdi Amini
12a3bb49b1 Use std::move on the enum to insert it into the pair to please MSVC
(I have no idea why is it needed)
Fixup for r267103

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267104 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 04:45:57 +00:00
Mehdi Amini
90c7bb067d Refactor IRObjectFile, extract a static CollectAsmUndefinedRefs() method to parse inline assembly (NFC)
I plan to call this from ThinLTOCodeGenerator.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267103 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 04:28:05 +00:00
Nicolai Haehnle
3441786e27 AMDGPU/SI: add llvm.amdgcn.ps.live intrinsic
Summary:
This intrinsic returns true if the current thread belongs to a live pixel
and false if it belongs to a pixel that we are executing only for derivative
computation. It will be used by Mesa to implement gl_HelperInvocation.

Note that for pixels that are killed during the shader, this implementation
also returns true, but it doesn't matter because those pixels are always
disabled in the EXEC mask.

This unearthed a corner case in the instruction verifier, which complained
about a v_cndmask 0, 1, exec, exec<imp-use> instruction. That's stupid but
correct code, so make the verifier accept it as such.

Reviewers: arsenm, tstellarAMD

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19191

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267102 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 04:04:08 +00:00
Craig Topper
758524fcea [AVX512] Teach lowering to use vplzcntd/q to implement 128/256-bit CTTZ_ZERO_UNDEF even without VLX support. We can just extend to 512-bits and extract like we do for CTLZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267100 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 03:22:38 +00:00
Duncan P. N. Exon Smith
5ab1a4f5d9 ValueMapper/Enumerator: Clean up code in post-order traversals, NFC
Re-layer the functions in the new (i.e., newly correct) post-order
traversals in ValueEnumerator (r266947) and ValueMapper (r266949).
Instead of adding a node to the worklist in a helper function and
returning a flag to say what happened, return the node itself.  This
makes the code way cleaner: the worklist is local to the main function,
there is no flag for an early loop exit (since we can cleanly bury the
loop), and it's perfectly clear when pointers into the worklist might be
invalidated.

I'm fixing both algorithms in the same commit to avoid repeating the
commit message; if you take the time to understand one the other should
be easy.  The diff itself isn't entirely obvious since the traversals
have some noise (i.e., things to do), but here's the high-level change:

    auto helper = [&WL](T *Op) {     auto helper = [](T **&I, T **E) {
                                 =>    while (I != E) {
      if (shouldVisit(Op)) {             T *Op = *I++;
        WL.push(Op, Op->begin());        if (shouldVisit(Op)) {
        return true;                       return Op;
      }                                }
      return false;                    return nullptr;
    };                               };
                                 =>
    WL.push(S, S->begin());          WL.push(S, S->begin());
    while (!empty()) {               while (!empty()) {
      auto *N = WL.top().N;            auto *N = WL.top().N;
      auto *&I = WL.top().I;           auto *&I = WL.top().I;
      bool DidChange = false;
      while (I != N->end())
        if (helper(*I++)) {      =>    if (T *Op = helper(I, N->end()) {
          DidChange = true;              WL.push(Op, Op->begin());
          break;                         continue;
        }                              }
      if (DidChange)
        continue;

      POT.push(WL.pop());        =>    POT.push(WL.pop());
    }                                }

Thanks to Mehdi for helping me find a better way to layer this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267099 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 02:33:06 +00:00
Gerolf Hoflehner
7c23aa2d8c [MachineCombiner] Support for floating-point FMA on ARM64
Evaluates fmul+fadd -> fmadd combines and similar code sequences in the
machine combiner. It adds support for float and double similar to the existing
integer implementation. The key features are:

- DAGCombiner checks whether it should combine greedily or let the machine
combiner do the evaluation. This is only supported on ARM64.
- It gives preference to throughput over latency: the heuristic used is
to combine always in loops. The targets decides whether the machine
combiner should optimize for throughput or latency.
- Supports for fmadd, f(n)msub, fmla, fmls patterns
- On by default at O3 ffast-math



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267098 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 02:15:19 +00:00
Teresa Johnson
acfba51b27 [ThinLTO] Remove unused/incomplete lazy summary reading support (NFC)
This removes the interfaces added (and not yet complete) to support
lazy reading of summaries. This support is not expected to be needed
since we are moving to a model where the full index is only being
traversed in the thin link step, instead of the back ends.

(The second part of this that I plan to do next is remove the
GlobalValueInfo from the ModuleSummaryIndex - it was mostly needed to
support lazy parsing of summaries. The index can instead reference the
summary structures directly.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267097 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 01:52:00 +00:00
NAKAMURA Takumi
14eb0b531d Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267096 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 01:33:50 +00:00
Nico Weber
b725c76f82 Try to fix UNRESOLVED: LLVM :: CodeGen/AArch64/arm64-regress-opt-cmp.s on bots.
This test used to write a .s file until r266971 fixed that.  But on most bots,
the .s file still exists.  Add an rm statement to clean up the bots.  In a few
days, this statement can go away again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267095 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 01:08:56 +00:00
Saleem Abdulrasool
817fdeb9cc ARM: fix test for Windows division
This was meant to be part of SVN r267080.  cbz cannot use a high register, which
would be silently truncated.  This has now been fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267092 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-22 01:03:38 +00:00
Dan Gohman
e0dd87a040 [WebAssembly] Limit alignment hints to natural alignment.
This follows the current binary format rules.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267082 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 23:59:48 +00:00
Saleem Abdulrasool
197563ef14 ARM: restrict register class for WIN__DBZCHK
WIN__DBZCHK will insert a CBZ instruction into the stream.  This instruction
reserves 3 bits for the condition register (rn).  As such, we must ensure that
we restrict the register to a low register.  Use the tGPR class instead of GPR
to ensure that this is properly constrained.  In debug builds, we would attempt
to use lr as a condition register which would silently get truncated with no
hint that the register selection was incorrect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267080 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 23:53:19 +00:00
Mike Aizatsky
aa724817e4 [sancov] using normalized filenames for blacklist checks.
Differential Revision: http://reviews.llvm.org/D19395

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267078 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 23:38:45 +00:00
David Blaikie
259641db60 Fix more -Wunused-variable in non-asserts build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267077 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 23:24:09 +00:00
Tim Northover
361618ec68 MachO: enable .data_region directives everywhere
We'd disabled them on x86 because back in the early days some host tools
couldn't handle the new load commands. This no longer holds: anyone capable of
deploying Clang should be able to deploy its copies of ar/ranlib/etc.

rdar://25254790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267075 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 23:00:17 +00:00
David Blaikie
12098d3b4a Fix some -Wunused-variable warnings in non-asserts builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267073 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 22:53:33 +00:00
Vedant Kumar
a0a870ff27 [Support] Fix Wcast-qual warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267072 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 22:40:59 +00:00
Reid Kleckner
a1d19be01d Fix PDB warnings and test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267071 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 22:37:55 +00:00
Derek Schuff
4913b3f2cf Improve error message reporting for MachineFunctionProperties
When printing the properties required by a pass, only print the
properties that are set, and not those that are clear (only properties
that are set are verified, clear properties are "don't-care").

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267070 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 22:19:24 +00:00
Amaury Sechet
cfbb8a788e Remove dead code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267069 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 22:17:39 +00:00
Zachary Turner
46d5ec0afd Fix -Wreturn-type warning with HAVE_DIA_SDK is false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267068 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 22:16:19 +00:00
Zachary Turner
9c2e16e35e Fix pdbdump-headers.test after guid format change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267067 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 22:13:25 +00:00
Zachary Turner
d192551402 Fix for case sensitive filename failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267066 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 22:08:27 +00:00
Mike Aizatsky
de4d323c44 Fixed flag description
Summary:
asan-use-after-return control feature we call use-after-return or
stack-use-after-return.

Reviewers: kcc, aizatsky, eugenis

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D19284

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267064 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 22:00:13 +00:00
Amaury Sechet
48c9c5be8d Remove various warnings. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267061 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 21:36:11 +00:00
Derek Bruening
3494767094 [esan] EfficiencySanitizer instrumentation pass
Summary:
Adds an instrumentation pass for the new EfficiencySanitizer ("esan")
performance tuning family of tools.  Multiple tools will be supported
within the same framework.  Preliminary support for a cache fragmentation
tool is included here.

The shared instrumentation includes:
+ Turn mem{set,cpy,move} instrinsics into library calls.
+ Slowpath instrumentation of loads and stores via callouts to
  the runtime library.
+ Fastpath instrumentation will be per-tool.
+ Which memory accesses to ignore will be per-tool.

Reviewers: eugenis, vitalybuka, aizatsky, filcab

Subscribers: filcab, vkalintiris, pcc, silvas, llvm-commits, zhaoqin, kcc

Differential Revision: http://reviews.llvm.org/D19167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267058 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-21 21:30:22 +00:00