Commit Graph

175 Commits

Author SHA1 Message Date
Owen Anderson
bf63022492 Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&.  At this point they almost behave like normal iterators!

Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 23:12:04 +00:00
Craig Topper
9f998de891 [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203220 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 09:26:03 +00:00
Benjamin Kramer
94ee55d4b3 Replace some unnecessary vector copies with references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-15 22:04:42 +00:00
Richard Sandiford
9608ed1311 Fix overly pessimistic shortcut in post-RA MachineLICM
Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers
and TermRegs.  When it sees a definition of R it adds all aliases of R
to the corresponding set, so that when it needs to test for membership
it only needs to test a single register, rather than worrying about
aliases there too.  E.g. the final candidate loop just has:

    unsigned Def = Candidates[i].Def;
    if (!PhysRegClobbers.test(Def) && ...) {

to test whether register Def is multiply defined.

However, there was also a shortcut in ProcessMI to make sure we didn't
add candidates if we already knew that they would fail the final test.
This shortcut was more pessimistic than the final one because it
checked whether _any alias_ of the defined register was multiply defined.
This is too conservative for targets that define register pairs.
E.g. on z, R0 and R1 are sometimes used as a pair, so there is a
128-bit register that aliases both R0 and R1.  If a loop used
R0 and R1 independently, and the definition of R0 came first,
we would be able to hoist the R0 assignment (because that used
the final test quoted above) but not the R1 assignment (because
that meant we had two definitions of the paired R0/R1 register
and would fail the shortcut in ProcessMI).

This patch just uses the same check for the ProcessMI shortcut as
we use in the final candidate loop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 09:11:13 +00:00
Craig Topper
9e639e8fd9 Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186098 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-11 16:22:38 +00:00
Benjamin Kramer
69e42dbd00 Split TargetLowering into a CodeGen and a SelectionDAG part.
This fixes some of the cycles between libCodeGen and libSelectionDAG. It's still
a complete mess but as long as the edges consist of virtual call it doesn't
cause breakage. BasicTTI did static calls and thus broke some build
configurations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-11 20:05:37 +00:00
Patrik Hagglund
860e7cdab9 Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.

Accordingly, change RegDefIter to contain MVTs instead of EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170140 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 18:45:35 +00:00
Patrik Hagglund
34525f9ac0 Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 11:14:33 +00:00
Patrik Hagglund
aa7744d75f Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.

Accordingly, change RegDefIter to contain MVTs instead of EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 09:31:43 +00:00
Chandler Carruth
d04a8d4b33 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 16:50:05 +00:00
Craig Topper
96601ca332 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 06:07:19 +00:00
Jakob Stoklund Olesen
396618b43a Switch all register list clients to the new MC*Iterator interface.
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01 23:28:30 +00:00
Jakob Stoklund Olesen
397fc4874e Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07 22:10:26 +00:00
Jakob Stoklund Olesen
71fbed45d9 Tweak MachineLICM heuristics for cheap instructions.
Allow cheap instructions to be hoisted if they are register pressure
neutral or better. This happens if the instruction is the last loop use
of another virtual register.

Only expensive instructions are allowed to increase loop register
pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 00:00:28 +00:00
Jakob Stoklund Olesen
8b560b8c48 Only check for PHI uses inside the current loop.
Hoisting a value that is used by a PHI in the loop will introduce a
copy because the live range is extended to cross the PHI.

The same applies to PHIs in exit blocks.

Also use this opportunity to make HasLoopPHIUse() non-recursive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 00:00:26 +00:00
Evan Cheng
d6c2355789 Post-ra LICM should take care not to hoist an instruction that would clobber a
register that's read by the preheader terminator.

rdar://11095580


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153492 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27 01:50:58 +00:00
Craig Topper
e4fd907e72 Use uint16_t to store register overlaps to reduce static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04 10:43:23 +00:00
Chad Rosier
921c9bd91f Fix 80-column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28 00:23:01 +00:00
Jakob Stoklund Olesen
0f7de3542f Revert r150288, "Allow Post-RA LICM to hoist reserved register reads."
This caused miscompilations on out-of-tree targets, and possibly i386 as
well.

I'll find some other way of hoisting %rip-relative loads from loops
containing calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17 16:40:44 +00:00
Jakob Stoklund Olesen
5637379000 Allow Post-RA LICM to hoist reserved register reads.
When using register masks, registers like %rip are clobbered by the
register mask. LICM should still be able to hoist instructions reading
%rip from a loop containing calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150288 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 00:44:19 +00:00
Jakob Stoklund Olesen
fd3d4cf0ef Don't read PreRegAlloc before it is initialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150286 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-11 00:40:36 +00:00
Andrew Trick
1dd8c8560d Codegen pass definition cleanup. No functionality.
Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:23:13 +00:00
Andrew Trick
9d41bd5c78 Move pass configuration out of pass constructors: MachineLICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150099 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:23:03 +00:00
Andrew Trick
9f17cf625d whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150098 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-08 21:23:00 +00:00
Jakob Stoklund Olesen
478a8a02bc Require non-NULL register masks.
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-02 23:52:57 +00:00
Jakob Stoklund Olesen
d0848a6398 Fix PR11829. PostRA LICM was too aggressive.
This fixes a typo in r148589.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 21:01:15 +00:00
Jakob Stoklund Olesen
39f6660193 Simplify debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148723 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 21:01:11 +00:00
Jakob Stoklund Olesen
a3c4ca9c7b Support register masks in MachineLICM.
Only PostRA LICM is affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:27:12 +00:00
Jakob Stoklund Olesen
c035c940a6 Extract method for detecting constant unallocatable physregs.
It is safe to move uses of such registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 22:34:08 +00:00
Evan Cheng
75fda5dcae 80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10 22:27:32 +00:00
Pete Cooper
3cfecf5cc2 Hoisted some loop invariant smallvector lookups out of a MachineLICM loop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 02:13:25 +00:00
Pete Cooper
acde91e273 Changed MachineLICM to use a worklist list MachineCSE instead of recursion.
Fixes <rdar://problem/10584116>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 02:05:40 +00:00
Evan Cheng
5a96b3dad2 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 07:15:52 +00:00
Evan Cheng
7c2a4a30e0 First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:12:01 +00:00
Owen Anderson
99aa14ff64 Rename MVT::untyped to MVT::Untyped to match similar nomenclature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 01:02:57 +00:00
Evan Cheng
73b5bb3865 Disable LICM speculation in high register pressure situation again now that Devang has fixed other issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 01:26:57 +00:00
Devang Patel
06e16bbec0 As Evan suggested, loads from constant pool are safe to speculate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 17:42:23 +00:00
Devang Patel
e6de9f30cb Add a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 17:31:18 +00:00
Evan Cheng
1025cce290 Constraint register class with constrainRegClass() to CSE a virtual into another. rdar://10293289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 19:50:12 +00:00
Devang Patel
6c15fec3c5 It is safe to speculate load from GOT. This fixes performance regression caused by r141689.
Radar 10281206.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142202 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 17:35:01 +00:00
Nick Lewycky
ea3abd5536 Tabs to spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 01:09:50 +00:00
Evan Cheng
7007e4c556 Disable machine LICM speculation check (for profitability) until I have time to investigate the regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 21:33:49 +00:00
Bill Wendling
a2e87912d8 Expand the check for a landing pad so that it looks at the basic block's
containing loop's header to see if that's a landing pad. If it is, then we don't
want to hoist instructions out of the loop and above the header.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 02:58:01 +00:00
Evan Cheng
7efba85d41 Fix r141744.
1. The speculation check may not have been performed if the BB hasn't had a load
   LICM candidate.
2. If the candidate would be CSE'ed, then go ahead and speculatively LICM the
   instruction even if it's in high register pressure situation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 00:09:14 +00:00
Evan Cheng
fad6287488 Refine r141689 with a tri-state variable.
Also teach MachineLICM to avoid "speculation" when register pressure is high.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 23:48:44 +00:00
Bill Wendling
c83693f5b0 N.B. This is with the new EH scheme:
The blocks with invokes have branches to the dispatch block, because that more
correctly models the behavior of the CFG. The dispatch of course has edges to
the landing pads. Those landing pads could contain invokes, which then have
branches back to the dispatch. This creates a loop. The machine LICM pass looks
at this loop and thinks it can hoist elements out of it. But because the
dispatch is an alternate entry point into the program, the hoisted instructions
won't be executed.

I wasn't able to get a testcase which was small and could reproduce all of the
time. The function_try_block.cpp in llvm-test was where this showed up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 22:42:31 +00:00
Devang Patel
2e35047947 Add dominance check for the instruction being hoisted.
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 18:09:58 +00:00
Devang Patel
db7334dbc5 Revert r141569 and r141576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:18:02 +00:00
Devang Patel
6b50bc9d88 If loop header is also loop exiting block then it may not be safe to hoist instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 20:32:03 +00:00
Devang Patel
9ac743a4ee Add dominance check for the instruction being hoisted.
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 19:09:20 +00:00