Commit Graph

66019 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
d0eeeeb558 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:15:00 +00:00
Jim Grosbach
0de6ab3c43 Add encoding information for the remainder of the generic arithmetic
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:11:26 +00:00
Bob Wilson
77f42b5278 PR8359: The ARM backend may end up allocating registers D16 to D31 when
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 16:22:47 +00:00
Eric Christopher
1541877941 Rework alloca handling so that we can load or store from casted
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 05:39:06 +00:00
Eric Christopher
14074e8ec4 Fix the last two commits to configure - configure is a generated file.
Made necessary edits to configure.ac and regenerated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 02:42:05 +00:00
Eric Christopher
5532433a57 Handle a wider arrangement of loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:43:21 +00:00
Cameron Esfahani
519c893c26 Fix spelling error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:21:05 +00:00
Dan Gohman
624218f5b4 Delete a redundant check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:19:24 +00:00
Dan Gohman
9b0e47efc6 More SmallVectorImpls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:15:27 +00:00
Dan Gohman
8de206c101 Shrink a SmallVector with a known maximum size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116278 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:13:43 +00:00
Dan Gohman
568a63db96 Constify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:12:29 +00:00
Dan Gohman
ebb1834e86 Use SmallVectorImpl in a bunch of places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:11:18 +00:00
Francois Pichet
b2b9b768ef Disable warning C4267 for MSVC. Otherwise it generate literally thousands of warnings when targeting x64. The warning occurs because int is 32 bit but size_t is 64 bit on Win64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 00:01:36 +00:00
Dan Gohman
c015723131 Add a simple testcase for tbaa.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:54:13 +00:00
Evan Cheng
08cec1ef27 More ARM scheduling itinerary fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:41:41 +00:00
Dan Gohman
633e702317 Support AA chaining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116264 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:39:34 +00:00
Dan Gohman
7c34730fb9 Fix the pass manager's search order for immutable passes, and make it
stop searching when it has found a match.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116262 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:19:01 +00:00
Jim Grosbach
42fac8ee3b MC machine encoding for simple aritmetic instructions that use a shifted
register operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:16:21 +00:00
Jason W Kim
17b443df43 Second set of ARM/MC/ELF changes.
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116257 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:01:44 +00:00
Dan Gohman
d3d2ddc78e Clang's #include handling apparently doesn't work for libstdc++'s
fenv.h. See PR6907 for details. Work around this in FEnv.h to fix
the seflhost build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116256 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 22:30:59 +00:00
Michael J. Spencer
e58d72009a Unit Tests: Missed this error. MSVC and clang didn't complain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116252 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 22:04:38 +00:00
Evan Cheng
60ff87914f Proper VST scheduling itineraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 22:03:18 +00:00
Eric Christopher
5f9e8b971b Use a sane mechanism for that assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116249 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 22:01:22 +00:00
Michael J. Spencer
4c099b8724 System: Add SwapByteOrder and update Support/MathExtras.h to use it.
This time correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116247 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:56:16 +00:00
Jakob Stoklund Olesen
31cc3ec330 Replace FindLiveRangeContaining() with getVNInfoAt() in LiveIntervalAnalysis.
This helps hiding the LiveRange class which really should be private.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116244 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:45:03 +00:00
Jim Grosbach
a1e2194f03 The assert() should reference to machine instr operand number, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:41:31 +00:00
Michael J. Spencer
af72684eea Revert "System: Add SwapByteOrder and update Support/MathExtras.h to use it."
This reverts commit 116234.

It compiled just fine with MSVC and clang...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:39:24 +00:00
Eric Christopher
050d16c2a9 We're not going to handle dynamic allocas anywhere else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:37:35 +00:00
Daniel Dunbar
1086c2b5da Change explicit search Apple specific code to only reference __eprintf on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116239 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:34:24 +00:00
Jim Grosbach
1a7233f9d0 Make sure to use the machine instruction operand number. It doesn't always
map one-to-one with the CodeGenInstruction operand number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:31:22 +00:00
Michael J. Spencer
12647eb3f5 Reduce dpendencies for SupportTests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:22:34 +00:00
Michael J. Spencer
5031e0d977 System: Add SwapByteOrder and update Support/MathExtras.h to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:22:22 +00:00
Eric Christopher
fb0b892f7e Make sure that the call stack adjustments have default operands. Also
leave custom lowerings for later.

Fixes some nightly tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:20:02 +00:00
Andrew Trick
0a434dbb91 PR8297
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116223 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:08:42 +00:00
Jakob Stoklund Olesen
4f9af2ef65 PowerPC varargs functions store live-in registers on the stack. Make sure we use
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:43:09 +00:00
Eric Christopher
8ff9a9da0a Found a bug turning this on by default. Disable again for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:26:21 +00:00
Eric Christopher
a3d210733a Remove now non-existent option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:21:21 +00:00
Eric Christopher
fa6b29dacd Fix help text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:15:02 +00:00
Eric Christopher
feadddd6b6 Change flag from Enable to Disable since we're enabled by default.
Also don't use fast-isel on non-darwin since it's untested.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 20:05:22 +00:00
Michael J. Spencer
bbb9ea7b70 Add KillTheDoctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116216 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 19:55:38 +00:00
Jim Grosbach
c4bd6fbf4b trailing whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 19:38:01 +00:00
Andrew Trick
1a2cf3b4d9 Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116214 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 19:02:04 +00:00
Jim Grosbach
62547267f0 More binary encoding stuff, taking advantage of the new "by name" operand
matching in tblgen to do the predicate operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116213 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:51:51 +00:00
Eric Christopher
a2efc5ff6e Turn on arm fast isel by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:48:18 +00:00
Jim Grosbach
01855071e2 When figuring out which operands match which encoding fields in an instruction,
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:25:51 +00:00
Jakob Stoklund Olesen
40ef4fe82a Properly handle reloading and spilling around partial redefines in
LocalRewriter.

This is a bit of a hack that adds an implicit use operand to model the
read-modify-write nature of a partial redef. Uses and defs are rewritten in
separate passes, and a single operand would never be processed twice.

<rdar://problem/8518892>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116210 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:10:36 +00:00
Chris Lattner
ffa0e71c33 remove dead prototype, PR8351
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116209 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 17:44:22 +00:00
Francois Pichet
1265776243 MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 11:36:19 +00:00
Eric Christopher
a1640d9ed9 Copy and pasteo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:40:05 +00:00
Eric Christopher
dccd2c3c43 Whitespace cleanup in ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 08:38:55 +00:00