7 Commits

Author SHA1 Message Date
Matthew Simpson
e40864cee2 [ARM, AArch64] Match additional patterns to ldN instructions
When matching an interleaved load to an ldN pattern, the interleaved access
pass checks that all users of the load are shuffles. If the load is used by an
instruction other than a shuffle, the pass gives up and an ldN is not
generated. This patch considers users of the load that are extractelement
instructions. It attempts to modify the extracts to use one of the available
shuffles rather than the load. After the transformation, the load is only used
by shuffles and will then be matched with an ldN pattern.

Differential Revision: http://reviews.llvm.org/D20250

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270142 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-19 21:39:00 +00:00
Matthew Simpson
d06ea8a8f4 [ARM, AArch64] Properly initialize InterleavedAccessPass
InterleavedAccessPass is an IR-level pass, so this change will enable testing
it with opt. This is part of D20250.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270101 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-19 20:08:32 +00:00
Chad Rosier
b08a82c043 Cleanup comments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268233 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-02 14:32:17 +00:00
Silviu Baranga
bbdc83dd12 [ARM][AArch64] Turn on by default interleaved access lowering
Summary:
Interleaved access lowering removes a memory operation and a
sequence of vector shuffles and replaces it with a series of
memory operations. This should be always beneficial.

This pass in only enabled on ARM/AArch64.

Reviewers: rengolin

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D12145

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246540 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-01 11:12:35 +00:00
Nico Rieck
3dd7bf5e76 Rename inst_range() to instructions() for consistency. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244248 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-06 19:10:45 +00:00
Hao Liu
fabf219603 [InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240760 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 04:38:21 +00:00
Hao Liu
41b3fe53ba [InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics.
E.g. An interleaved load (Factor = 2):
        %wide.vec = load <8 x i32>, <8 x i32>* %ptr
        %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
        %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend.

E.g. An interleaved store (Factor = 3):
        %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
        store <12 x i32> %i.vec, <12 x i32>* %ptr
It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend.

Differential Revision: http://reviews.llvm.org/D10533


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240751 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-26 02:10:27 +00:00