5 Commits

Author	SHA1	Message	Date
Matthias Braun	66489736bf	MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. ... Specifying isSSA is an extra line at best and results in invalid MI at worst. Compute the value instead. Differential Revision: http://reviews.llvm.org/D22722 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279600 91177308-0d34-0410-b5e6-96231b3b80d8	2016-08-24 01:32:41 +00:00
Matthias Braun	3346c15107	llc: Add support for -run-pass none ... This does not schedule any passes besides the ones necessary to construct and print the machine function. This is useful to test .mir file reading and printing. Differential Revision: http://reviews.llvm.org/D22432 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275664 91177308-0d34-0410-b5e6-96231b3b80d8	2016-07-16 02:24:59 +00:00
Quentin Colombet	3d35f0d482	[MIR] Print on the given output instead of stderr. ... Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275314 91177308-0d34-0410-b5e6-96231b3b80d8	2016-07-13 20:36:03 +00:00
Justin Lebar	3a1cea0888	When printing MIR, output to errs() rather than outs(). ... Summary: Without this, this command $ llvm-run llc -stop-after machine-cp -o - <( echo '' ) outputs an error, because we close stdout twice -- once when closing the file opened for "-o", and again when closing outs(). Also clarify in the outs() definition that you can't ever call it if you want to open your own raw_fd_ostream on stdout. Reviewers: jroelofs, tstellarAMD Subscribers: jholewinski, qcolombet, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17422 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261286 91177308-0d34-0410-b5e6-96231b3b80d8	2016-02-19 00:18:46 +00:00
Alex Lorenz	eecbba2d64	Fix PR 24724 - The implicit register verifier shouldn't assume certain operand ... order. The implicit register verifier in the MIR parser should only check if the instruction's default implicit operands are present in the instruction. It should not check the order in which they occur. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247283 91177308-0d34-0410-b5e6-96231b3b80d8	2015-09-10 14:04:34 +00:00