Commit Graph

100179 Commits

Author SHA1 Message Date
Sjoerd Meijer
b9ae988ece AArch64AsmParser: don't try to parse “[1]” for non-vector register operands
There are no instructions that have "[1]" as part of the assembly string;
FMOVXDhighr is out of date. This removes dead code.

Differential Revision: https://reviews.llvm.org/D30165


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296327 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-27 10:51:11 +00:00
Konstantin Zhuravlyov
9995ddddac [AMDGPU] Runtime metadata fixes:
- Verify that runtime metadata is actually valid runtime metadata when assembling, otherwise we could accept the following when assembling, but ocl runtime will reject it:
    .amdgpu_runtime_metadata
    { amd.MDVersion: [ 2, 1 ], amd.RandomUnknownKey, amd.IsaInfo: ...
  - Make IsaInfo optional, and always emit it.

Differential Revision: https://reviews.llvm.org/D30349


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296324 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-27 07:55:17 +00:00
Craig Topper
08d480dc77 [X86] Check for less than 0 rather than explicit compare with -1. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296321 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-27 06:05:30 +00:00
Xin Tong
e76fd06806 Update comments. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296298 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 19:08:44 +00:00
Daniel Jasper
e5e8f2aec1 Revert "[CGP] Split some critical edges coming out of indirect branches"
This reverts commit r296149 as it leads to crashes when compiling for
PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296295 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 11:09:12 +00:00
Davide Italiano
1aaf55cfbf [LoopDeletion] Modernize and simplify a bit. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296294 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 07:08:20 +00:00
Craig Topper
ca75ea33bc [X86] Fix execution domain for cmpss/sd instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296293 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 06:45:59 +00:00
Craig Topper
bcfde2ad75 [AVX-512] Fix execution domain for scalar commutable min/max instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296292 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 06:45:56 +00:00
Craig Topper
d9d761585e [AVX-512] Fix execution domain for vmovhpd/lpd/hps/lps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296291 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 06:45:54 +00:00
Craig Topper
f46e01bb23 [AVX-512] Fix the execution domain for AVX-512 integer broadcasts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296290 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 06:45:51 +00:00
Craig Topper
b64325c5da [AVX-512] Disable the redundant patterns in the VPBROADCASTBr_Alt and VPBROADCASTWr_Alt instructions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296289 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 06:45:48 +00:00
Craig Topper
b1620f1be0 [AVX-512] Fix execution domain for VPMADD52 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296288 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 06:45:45 +00:00
Craig Topper
3703247296 [AVX-512] Fix the execution domain for VSCALEF instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296286 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 06:45:40 +00:00
Craig Topper
bb0ec0e4f5 [AVX-512] Fix execution domain of scalar VRANGE/REDUCE/GETMANT with sae.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296285 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 06:45:37 +00:00
Craig Topper
914a8e7fd7 [X86] Fix the execution domain for scalar SQRT intrinsic instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296284 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 06:45:35 +00:00
Xin Tong
650a66fb4c [SCCP] Remove manual folding of terminator instructions.
Summary:
BranchInst, SwitchInst (with non-default case) with Undef as input is not
possible at this point. As we always default-fold terminator to one target in
ResolvedUndefsIn and set the input accordingly.

So we should only have constantint/blockaddress here.

If ConstantFoldTerminator fails, that could mean 2 things.

1. ConstantFoldTerminator is doing something unexpected, i.e. not folding on constantint
or blockaddress and not making blocks that should be dead dead.
2. This is not a terminator on constantint or blockaddress. Its on a constant or
overdefined, then this block should not be dead.

In both cases, we should assert.

Reviewers: davide, efriedma, sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30381

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296281 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 02:11:24 +00:00
Nirav Dave
b89cc7e5e3 Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
This reverts commit r296252 until 256-bit operations are more efficiently generated in X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296279 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 01:27:32 +00:00
Eric Christopher
0ef3663fb8 vec perm can go down either pipeline on P8.
No observable changes, spotted while looking at the scheduling description.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296277 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-26 00:11:58 +00:00
Sanjoy Das
9b2526d03d [ValueTracking] Don't do an unchecked shift in ComputeNumSignBits
Summary:
Previously we used to return a bogus result, 0, for IR like `ashr %val,
-1`.

I've also added an assert checking that `ComputeNumSignBits` at least
returns 1.  That assert found an already checked in test case where we
were returning a bad result for `ashr %val, -1`.

Fixes PR32045.

Reviewers: spatel, majnemer

Reviewed By: spatel, majnemer

Subscribers: efriedma, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D30311

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296273 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 20:30:45 +00:00
Simon Pilgrim
95d021ba68 [APInt] Add APInt::extractBits() method to extract APInt subrange (reapplied)
The current pattern for extract bits in range is typically:

Mask.lshr(BitOffset).trunc(SubSizeInBits);

Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation of memory for the temporary variable.

This is another of the compile time issues identified in PR32037 (see also D30265).

This patch adds the APInt::extractBits() helper method which avoids the temporary memory allocation.

Differential Revision: https://reviews.llvm.org/D30336

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296272 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 20:01:58 +00:00
Craig Topper
955b35337f [AVX-512] Fix the execution domain for scalar FMA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296271 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 19:36:28 +00:00
Craig Topper
5d138fe5d3 [AVX-512] Fix the execution domain on some instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296270 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 19:18:11 +00:00
Craig Topper
d63ab8f4ea [AVX-512] Remove unnecessary masked versions of VCVTSS2SD and VCVTSD2SS using the scalar register class. We only have patterns for the masked intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296264 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 18:43:42 +00:00
Craig Topper
6a0edd3bec [ExecutionDepsFix] Don't make copies of LiveReg objects when collecting operands for soft instructions
Summary:
While collecting operands we make copies of the LiveReg objects which are stored in the LiveRegs array. If the instruction uses the same register multiple times we end up with multiple copies. Later we iterate through the collected list of LiveReg objects and merge DomainValues. In the process of doing this the merge function can change the contents of the original LiveReg object in the LiveRegs array, but not the copies that have been made. So when we get to the second usage of the register we end up seeing a stale copy of the LiveReg object.

To fix this I've stopped copying and now just store a pointer to the original LiveReg object. Another option might be to avoid adding the same register to the Regs array twice, but this approach seemed simpler.

The included test case exposes this bug due to an AVX-512 masked OR instruction using the same register for the passthru operand and one of the inputs to the OR operation.

Fixes PR30284.

Reviewers: RKSimon, stoklund, MatzeB, spatel, myatsina

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30242

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296260 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 18:12:25 +00:00
Artyom Skrobov
cc3dbb4073 No need to copy the variable [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296259 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 17:18:09 +00:00
NAKAMURA Takumi
96678fa6d8 Revert r296215, "[PDB] General improvements to Stream library." and followings.
r296215, "[PDB] General improvements to Stream library."
r296217, "Disable BinaryStreamTest.StreamReaderObject temporarily."
r296220, "Re-enable BinaryStreamTest.StreamReaderObject."
r296244, "[PDB] Disable some tests that are breaking bots."
r296249, "Add static_cast to silence -Wc++11-narrowing."

std::errc::no_buffer_space should be used for OS-oriented errors for socket transmission.
(Seek discussions around llvm/xray.)

I could substitute s/no_buffer_space/others/g, but I revert whole them ATM.

Could we define and use LLVM errors there?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296258 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 17:04:23 +00:00
Victor Leschuk
532cb32214 [DebugInfo] Skip implicit_const attributes when dumping .debug_info. NFC.
When dumping .debug_info section we loop through all attributes mentioned in
.debug_abbrev section and dump values using DWARFFormValue::extractValue().
We need to skip implicit_const attributes here as their values are not
really located in .debug_info but directly in .debug_abbrev. This patch fixes
triggered assert() in DWARFFormValue::extractValue() caused by trying to
access implicit_const values from .debug_info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296253 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 13:15:57 +00:00
Nirav Dave
32147cef64 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.

    * Simplify Consecutive Merge Store Candidate Search

    Now that address aliasing is much less conservative, push through
    simplified store merging search and chain alias analysis which only
    checks for parallel stores through the chain subgraph. This is cleaner
    as the separation of non-interfering loads/stores from the
    store-merging logic.

    When merging stores search up the chain through a single load, and
    finds all possible stores by looking down from through a load and a
    TokenFactor to all stores visited.

    This improves the quality of the output SelectionDAG and the output
    Codegen (save perhaps for some ARM cases where we correctly constructs
    wider loads, but then promotes them to float operations which appear
    but requires more expensive constant generation).

    Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)

    Additional Minor Changes:

      1. Finishes removing unused AliasLoad code

      2. Unifies the chain aggregation in the merged stores across code
         paths

      3. Re-add the Store node to the worklist after calling
         SimplifyDemandedBits.

      4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
         arbitrary, but seems sufficient to not cause regressions in
         tests.

      5. Remove Chain dependencies of Memory operations on CopyfromReg
         nodes as these are captured by data dependence

      6. Forward loads-store values through tokenfactors containing
          {CopyToReg,CopyFromReg} Values.

      7. Peephole to convert buildvector of extract_vector_elt to
         extract_subvector if possible (see
         CodeGen/AArch64/store-merge.ll)

      8. Store merging for the ARM target is restricted to 32-bit as
         some in some contexts invalid 64-bit operations are being
         generated. This can be removed once appropriate checks are
         added.

    This finishes the change Matt Arsenault started in r246307 and
    jyknight's original patch.

    Many tests required some changes as memory operations are now
    reorderable, improving load-store forwarding. One test in
    particular is worth noting:

      CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
      forwarding converts a load-store pair into a parallel store and
      a memory-realized bitcast of the same value. However, because we
      lose the sharing of the explicit and implicit store values we
      must create another local store. A similar transformation
      happens before SelectionDAG as well.

    Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296252 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 11:43:58 +00:00
Xin Tong
51d41dcad2 Empty line. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296250 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 08:10:28 +00:00
Junmo Park
c236d01938 Minor code cleanup. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296222 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 01:50:45 +00:00
Akira Hatanaka
1613664c57 Remove redundant code. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296219 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 00:59:49 +00:00
Akira Hatanaka
cf0aa991df Clean up ObjCARCOpts.cpp. NFC.
I removed unused functions and variables and moved variables closer to
their uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296218 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 00:53:38 +00:00
Zachary Turner
5433d115a4 [PDB] General improvements to Stream library.
This adds various new functionality and cleanup surrounding the
use of the Stream library.  Major changes include:

* Renaming of all classes for more consistency / meaningfulness
* Addition of some new methods for reading multiple values at once.
* Full suite of unit tests for reader / writer functionality.
* Full set of doxygen comments for all classes.
* Streams now store their own endianness.
* Fixed some bugs in a few of the classes that were discovered
  by the unit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296215 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 00:44:30 +00:00
Zachary Turner
40ea28492e [PDB] Rename Stream related source files.
This is part of a larger effort to get the Stream code moved
up to Support.  I don't want to do it in one large patch, in
part because the changes are so big that it will treat everything
as file deletions and add, losing history in the process.
Aside from that though, it's just a good idea in general to
make small changes.

So this change only changes the names of the Stream related
source files, and applies necessary source fix ups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296211 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 00:33:34 +00:00
Easwaran Raman
da9c4a6e9a [InlineCost] Move the code in isGEPOffsetConstant to a lambda.
Differential revision: https://reviews.llvm.org/D30112

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296208 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 00:10:22 +00:00
Junmo Park
8435ebc657 Minor code cleanup. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296207 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 00:08:53 +00:00
Rong Xu
dd2b6c53e8 [PGO] Directory name stripping in global identifier for static functions
Current internal option -static-func-full-module-prefix keeps all the
directory path the profile counter names for static functions. The default
of this option is false. This strips the directory names from the source
filename which is problematic:

(1) it creates linker errors for profile-generation compilation, exposed in
our internal benchmarks. We are seeing messages like
"warning: relocation refers to discarded section".
This is due to the name conflicts after the stripping.

(2) the stripping only applies to getPGOFuncName.
Current Thin-LTO module importing for the indirect-calls assumes
the source directory name not being stripped. Current default value
for this option can potentially prevent some inter-module
indirect-call-promotions.

This patch turns the default value for -static-func-full-module-prefix to true.

The second part of the patch is to have an alternative implementation under
 the internal option -static-func-strip-dirname-prefix=<value>

This options specifies level of directories to be stripped from the source
filename. Using a large value as the parameter has the same effect as
-static-func-full-module-prefix.

Differential Revision: http://reviews.llvm.org/D29512



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296206 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-25 00:00:36 +00:00
Dan Gohman
8f5a7d69cc [WebAssembly] Add support for using a wasm global for the stack pointer.
This replaces the __stack_pointer variable which was allocated in linear
memory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296201 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 23:46:05 +00:00
Krzysztof Parzyszek
cdc2ace692 [Hexagon] Undo shift folding where it could simplify addressing mode
For example, avoid (single shift):
  r0 = and(##536870908,lsr(r0,#3))
  r0 = memw(r1+r0<<#0)

in favor of (two shifts):
  r0 = lsr(r0,#5)
  r0 = memw(r1+r0<<#2)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296196 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 23:34:24 +00:00
Dan Gohman
53ff96ab08 [WebAssembly] Basic support for Wasm object file encoding.
With the "wasm32-unknown-unknown-wasm" triple, this allows writing out
simple wasm object files, and is another step in a larger series toward
migrating from ELF to general wasm object support. Note that this code
and the binary format itself is still experimental.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296190 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 23:18:00 +00:00
Krzysztof Parzyszek
d2a98e0ac0 [Hexagon] Prettify code in HexagonDAGToDAGISel::Select
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296187 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 23:00:40 +00:00
Wei Ding
5d1e915557 AMDGPU : Replace FMAD with FMA when denormals are enabled.
Differential Revision: http://reviews.llvm.org/D29958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296186 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 23:00:29 +00:00
Stanislav Mekhanoshin
fef0dbe59c Revert "Correct register pressure calculation in presence of subregs"
This reverts commit r296009. It broke one out of tree target and also
does not account for all partial lines added or removed when calculating
PressureDiff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296182 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 21:56:16 +00:00
Evgeniy Stepanov
89efd71a88 Disallow redefinition of section symbols.
Differential Revision: https://reviews.llvm.org/D30235

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296180 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 21:44:58 +00:00
Evgeniy Stepanov
5982b2c089 Initialize MCContext::InlineSrcMgr in the constructor.
Found with ASan (and a local source change) on test/CodeGen/XCore/section-name.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296179 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 21:44:52 +00:00
Tim Northover
e3a136c5b5 GlobalISel: check for CImm rather than Imm on G_CONSTANTs.
All G_CONSTANTS created by the MachineIRBuilder have an operand of type CImm
(i.e. a ConstantInt), so that's what the selector needs to look for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296176 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 21:21:38 +00:00
Dan Gohman
3d2ef31552 [WebAssembly] Handle f16 in fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296172 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 21:05:35 +00:00
Xin Tong
8ff565073e Fix Indentation. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296169 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 20:59:26 +00:00
Eli Friedman
0ee8e563c9 [CodeGenPrepare] Make -addr-sink-using-gep work with address spaces.
When we construct addressing modes, we use isNoopAddrSpaceCast to ignore
addrspacecast instructions. Make sure we insert the correct addrspacecast
when we reconstruct the addressing mode.

Differential Revision: https://reviews.llvm.org/D30114



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296167 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 20:51:36 +00:00
Yaxun Liu
3afc883be9 [InstCombine] Fix bug in pointer replacement
This optimisation was crashing when there was a chain of more than one bitcast
instruction to replace, as a result of the changes in D27283.

Patch by James Price.

Differential Revision: https://reviews.llvm.org/D30347


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296163 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-24 20:27:25 +00:00