29 Commits

Author SHA1 Message Date
Valery Pykhtin
9364829511 [AMDGPU] fix failure on printing of non-existing instruction operands.
Differential revision: https://reviews.llvm.org/D23323

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278665 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-15 10:56:48 +00:00
Valery Pykhtin
d27913ee68 Revert "[AMDGPU] fix failure on printing of non-existing instruction operands."
This reverts revision 278333, newly added test failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278336 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 14:22:05 +00:00
Valery Pykhtin
3876e2e984 [AMDGPU] fix failure on printing of non-existing instruction operands.
Differential revision: https://reviews.llvm.org/D23323

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278333 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 13:49:46 +00:00
Matt Arsenault
1a8f788ef1 AMDGPU: Remove unnecessary string usage in AsmPrinter
Registers are printed a lot, so don't create temporary
std::strings. Using char instead of a string to an ostream
saves a function call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274581 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-05 22:06:56 +00:00
Sam Kolton
bc0e31263e [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning in AMDGPUOperand.
Summary:
sext() modifier is supported in SDWA instructions only for integer operands. Spec is unclear should integer operands support abs and neg modifiers with sext - for now they are not supported.
Renamed InputModsWithNoDefault to FloatInputMods. Added SextInputMods for operands that support sext() modifier.
Added AMDGPUOperand::Modifier struct to handle register and immediate modifiers.
Code cleaning in AMDGPUOperand class: organize method in groups (render-, predicate-methods...).

Reviewers: vpykhtin, artem.tamazov, tstellarAMD

Subscribers: arsenm, kzhuravl

Differential Revision: http://reviews.llvm.org/D20968

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272384 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-10 09:57:59 +00:00
Artem Tamazov
cf3177d552 [AMDGPU][llvm-mc] s_getreg/setreg* - hwreg - factor out strings/literals etc.
Hwreg(...) syntax implementation unified with sendmsg(...).
Common strings moved to Utils
MathExtras.h functionality utilized.
Added missing build dependency in Disassembler.

Differential Revision: http://reviews.llvm.org/D20381

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270871 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-26 17:00:33 +00:00
Jan Vesely
7417b1b88a AMDGPU: Add support for MCExpr to instruction printer
Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269477 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 20:39:24 +00:00
Artem Tamazov
ea912da38b [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.
Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax
in s_sendmsg and s_sendmsghalt instructions.
The syntax matches the SP3 assembler/disassembler rules.
That is why implicit inputs (like M0 and EXEC) are not printed
to disassembly output anymore.

sendmsg(...) allows only known message types and attributes,
even if literals are used instead of symbolic names.
However, raw literal (without "sendmsg") still can be used,
and that allows for any 16-bit value.

Tests updated/added.

Differential Revision: http://reviews.llvm.org/D19596

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268762 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-06 17:48:48 +00:00
Artem Tamazov
f3487e82c4 Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD."
Previously reverted by r267752.

r267733 review:
Differential Revision: http://reviews.llvm.org/D19342

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268066 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 17:04:50 +00:00
Nikolay Haustov
02cd01c121 AMDGPU/SI: Assembler: Unify parsing/printing of operands.
Summary:
The goal is for each operand type to have its own parse function and
at the same time share common code for tracking state as different
instruction types share operand types (e.g. glc/glc_flat, etc).

Introduce parseAMDGPUOperand which can parse any optional operand.
DPP and Clamp/OMod have custom handling for now. Sam also suggested
to have class hierarchy for operand types instead of table. This
can be done in separate change.

Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps,
parseMubufOptionalOps, parseDPPOptionalOps.
Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class.
Rename AsmMatcher/InstPrinter methods accordingly.
Print immediate type when printing parsed immediate operand.
Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3).
Update tests.

Reviewers: tstellarAMD, SamWot, artem.tamazov

Subscribers: qcolombet, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19584

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268015 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 09:02:30 +00:00
Chad Rosier
8d960539d9 Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD."
This reverts commit r267733 due to a -Werror,-Wunused-function error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267752 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-27 18:29:11 +00:00
Artem Tamazov
7daa491b87 [AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.
Added support of TTMP quads.
Reworked M0 exclusion machinery for SMRD and similar instructions
to enable usage of TTMP registers in those instructions as destinations.
Tests added.

Differential Revision: http://reviews.llvm.org/D19342

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267733 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-27 16:20:23 +00:00
Artem Tamazov
d94d7faf07 [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.
Possibility to specify code of hardware register kept.
Disassemble to symbolic name, if name is known.
Tests updated/added.

Differential Revision: http://reviews.llvm.org/D19335

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267724 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-27 15:17:03 +00:00
Sam Kolton
3ca62aa938 [AMDGPU] Assembler: basic support for SDWA instructions
Support for SDWA instructions for VOP1 and VOP2 encoding.
Not done yet:
  - converters for support optional operands and modifiers
  - VOPC
  - sext() modifier
  - intrinsics
  - VOP2b (see vop_dpp.s)
  - V_MAC_F32 (see vop_dpp.s)

Differential Revision: http://reviews.llvm.org/D19360

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267553 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-26 13:33:56 +00:00
Artem Tamazov
2bc6d42753 [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.
Added hwreg(reg[,offset,width]) syntax.
Default offset = 0, default width = 32.
Possibility to specify 16-bit immediate kept.
Added out-of-range checks.
Disassembling is always to hwreg(...) format.
Tests updated/added.

Differential Revision: http://reviews.llvm.org/D19329

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267410 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-25 14:13:51 +00:00
Artem Tamazov
075abcbd06 [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)git status
Tests added along with implemented feature.
Note that there is a small leftover of unecessary MI sheduling issue
(more info in the review). CodeGen/AMDGPU/salu-to-valu.ll updated to fix
the false regression.

TODO: Support for TTMP quads, comma-separated syntax in "[]" and more.

Differential Revision: http://reviews.llvm.org/D17825

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266205 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-13 16:18:41 +00:00
Sam Kolton
5460c31240 [AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3
Review: http://reviews.llvm.org/D18267

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263789 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-18 15:35:51 +00:00
Matt Arsenault
7137d0dce6 AMDGPU: R600 code splitting cleanup
Move a few functions only used by R600 to R600 specific code,
fix header macros to stop using R600, mark classes as final.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263204 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-11 08:00:27 +00:00
Teresa Johnson
9925f81075 Fix build error due to unsigned compare >= 0 in r263008 (NFC)
Fixes error from building with clang:

/usr/local/google/home/tejohnson/llvm/llvm_15/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp:407:12:
error: comparison of unsigned expression >= 0 is always true
[-Werror,-Wtautological-compare]
  if ((Imm >= 0x000) && (Imm <= 0x0ff)) {
         ~~~ ^  ~~~~~

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263014 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-09 14:58:23 +00:00
Sam Kolton
6e4c55e686 [AMDGPU] Assembler: Support DPP instructions.
Supprot DPP syntax as used in SP3 (except several operands syntax).
Added dpp-specific operands in td-files.
Added DPP flag to TSFlags to determine if instruction is dpp in InstPrinter.
Support for VOP2 DPP instructions in td-files.
Some tests for DPP instructions.

ToDo:
  - VOP2bInst:
    - vcc is considered as operand
    - AsmMatcher doesn't apply mnemonic aliases when parsing operands
  - v_mac_f32
  - v_nop
  - disable instructions with 64-bit operands
  - change dpp_ctrl assembler representation to conform sp3

Review: http://reviews.llvm.org/D17804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263008 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-09 12:29:31 +00:00
Nikolay Haustov
d129fa6931 [AMDGPU] Disassembler code refactored + error messages.
Idea behind this change is to make code shorter and as much common for all targets as possible. Let's even accept more code than is valid for a particular target, leaving it for the assembler to sort out.

64bit instructions decoding added.

Error\warning messages on unrecognized instructions operands added, InstPrinter allowed to print invalid operands helping to find invalid/unsupported code.

The change is massive and hard to compare with previous version, so it makes sense just to take a look on the new version. As a bonus, with a few TD changes following, it disassembles the majority of instructions. Currently it fully disassembles >300K binary source of some blas kernel.

Previous TODOs were saved whenever possible.

Patch by: Valery Pykhtin

Differential Revision: http://reviews.llvm.org/D17720

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262332 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-01 13:57:29 +00:00
Nikolay Haustov
1c038cf2fa [AMDGPU] Assembler: Basic support for MIMG
Add parsing and printing of image operands. Matches legacy sp3 assembler.
Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last.
Update SITargetLowering for new order.
Add basic MC test.
Update CodeGen tests.

Review: http://reviews.llvm.org/D17574

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261995 91177308-0d34-0410-b5e6-96231b3b80d8
2016-02-26 09:51:05 +00:00
Tom Stellard
641de45f36 AMDGPU: waitcnt operand fixes
Summary:
Allow lgkmcnt up to 0xF (hardware allows that).
Fix mask for ExpCnt in AMDGPUInstPrinter.

Reviewers: tstellarAMD, arsenm

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D16314

Patch by: Nikolay Haustov

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@259059 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-28 17:13:44 +00:00
Chris Bieneman
caeade4234 Remove autoconf support
Summary:
This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html

"I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened."
- Obi Wan Kenobi

Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark

Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits

Differential Revision: http://reviews.llvm.org/D16471

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@258861 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-26 21:29:08 +00:00
Craig Topper
30e7d038e9 Remove extra forward declarations and scrub includes for all in tree InstPrinters. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256427 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-25 22:10:01 +00:00
Matt Arsenault
481eaf3a10 AMDGPU: Fix parsing of 32-bit literals with sign bit set
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251132 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-23 18:07:58 +00:00
NAKAMURA Takumi
09c0ea51ca Untabify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248264 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 11:15:07 +00:00
Tom Stellard
bfc6c664fc AMDGPU: s/R600/AMDGPU/ in the Makefiles
Now the library names in the Makefiles match the library names in
LLVMBuild.txt.

This should hopefully fix the remaining bot failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239661 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 05:11:14 +00:00
Tom Stellard
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00