Commit Graph

151023 Commits

Author SHA1 Message Date
Simon Dardis
349de318a7 [mips] Refine the condition for when to use CALL16 vs a GOT displacement.
Borrow from the logic for 'jal' in MipsAsmParser::processInstruction
and add the extra condition of bypassing CALL16 if the destination symbol
is an ELF symbol with STB_LOCAL binding.

Patch by: John Baldwin

Reviewers: sdardis

Differential Revision: https://reviews.llvm.org/D33999


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306387 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 10:11:11 +00:00
Diana Picus
99b52fe13c [ARM] GlobalISel: Support G_SELECT for i32
* Mark as legal for (s32, i1, s32, s32)
* Map everything into GPRs
* Select to two instructions: a CMP of the condition against 0, to set
  the flags, and a MOVCCr to select between the two inputs based on the
  flags that we've just set

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306382 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 09:19:51 +00:00
Ayal Zaks
84b5668c17 Recommitting 306331.
Undoing revert 306338 after fixed bug: add metadata to the load instead of the
reverse shuffle added to it, retaining the original ValueMap implementation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306381 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 08:41:19 +00:00
Hiroshi Inoue
27952de6ca [PowerPC] fix incorrect processor name for -mcpu in a test case
to surpress warnings. ppc970 should be 970 (or g5)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306380 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 08:35:35 +00:00
Chandler Carruth
7df0651976 [SROA] Fix PR32902 by more carefully propagating !nonnull metadata.
This is based heavily on the work done ni D34285. I mostly wanted to do
test cleanup for the author to save them some time, but I had a really
hard time understanding why it was so hard to write better test cases
for these issues.

The problem is that because SROA does a second rewrite of the loads and
because we *don't* propagate !nonnull for non-pointer loads, we first
introduced invalid !nonnull metadata and then stripped it back off just
in time to avoid most ways of this PR manifesting. Moving to the more
careful utility only fixes this by changing the predicate to look at the
new load's type rather than the target type. However, that *does* fix
the bug, and the utility is much nicer including adding range metadata
to model the nonnull property after a conversion to an integer.

However, we have bigger problems because we don't actually propagate
*range* metadata, and the utility to do this extracted from instcombine
isn't really in good shape to do this currently. It *only* handles the
case of copying range metadata from an integer load to a pointer load.
It doesn't even handle the trivial cases of propagating from one integer
load to another when they are the same width! This utility will need to
be beefed up prior to using in this location to get the metadata to
fully survive.

And even then, we need to go and teach things to turn the range metadata
into an assume the way we do with nonnull so that when we *promote* an
integer we don't lose the information.

All of this will require a new test case that looks kind-of like
`preserve-nonnull.ll` does here but focuses on range metadata. It will
also likely require more testing because it needs to correctly handle
changes to the integer width, especially as SROA actively tries to
change the integer width!

Last but not least, I'm a little worried about hooking the range
metadata up here because the instcombine logic for converting from
a range metadata *to* a nonnull metadata node seems broken in the face
of non-zero address spaces where null is not mapped to the integer `0`.
So that probably needs to get fixed with test cases both in SROA and in
instcombine to cover it.

But this *does* extract the core PR fix from D34285 of preventing the
!nonnull metadata from being propagated in a broken state just long
enough to feed into promotion and crash value tracking.

On D34285 there is some discussion of zero-extend handling because it
isn't necessary. First, the new load size covers all of the non-undef
(ie, possibly initialized) bits. This may even extend past the original
alloca if loading those bits could produce valid data. The only way its
valid for us to zero-extend an integer load in SROA is if the original
code had a zero extend or those bits were undef. And we get to assume
things like undef *never* satifies nonnull, so non undef bits can
participate here. No need to special case the zero-extend handling, it
just falls out correctly.

The original credit goes to Ariel Ben-Yehuda! I'm mostly landing this to
save a few rounds of trivial edits fixing style issues and test case
formulation.

Differental Revision: D34285

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306379 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 08:32:03 +00:00
Vassil Vassilev
9767b5aee6 Add missing forward declaraion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306376 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 08:10:28 +00:00
Nicolai Haehnle
7ca35760c5 AMDGPU: M0 operands to spill/restore opcodes are dead
Summary:
With scalar stores, M0 is clobbered and therefore marked as implicitly
defined. However, it is also dead.

This fixes an assertion when the Greedy Register Allocator decides to
optimize a spill/restore pair away again (via tryHintsRecoloring).

Reviewers: arsenm

Subscribers: qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D33319

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306375 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 08:04:13 +00:00
Ayman Musa
1921b1c5ed [TableGen] Fix bug in TableGen CodeGenPatterns when adding variants of the patterns.
All patterns reside in a std::vector container, where new variants are added to it using the standard library's emplace_back function.
When calling this with a new element while there is no enough allocated space, a bigger space is allocated and all the old info in the small vector is copied to the newly allocated vector, then the old vector is freed.
The problem is that before doing this "copying", we take a reference of one of the elements in the old vector, and after the "copying" we add it to the new vector.
As the old vector is freed after the copying, the reference now does not point to a valid element.

Added new function to the API of CodeGenDAGPatterns class to return the same information as a copy in order to avoid this issue.

This was revealed in rL305465 that added many patterns and forced the reallocation of the vector which caused crashes in windows bots.

Differential Revision: https://reviews.llvm.org/D34341



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306371 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 07:10:20 +00:00
Igor Breger
5d353d4750 [GlobalISel][X86] Add fp32/62 legalizer, regbank-select, selection tests for G_FADD, G_FSUB, G_FMUL, G_FDIV. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306370 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 07:01:54 +00:00
Galina Kistanova
025f924a12 Fixed the warning introduced by r306289 to make ubuntu-gcc7.1-werror bot green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306369 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 06:58:57 +00:00
Mikael Holmen
029ab41a28 [Reassociate] Make sure EraseInst sets MadeChange
Summary:
EraseInst didn't report that it made IR changes through MadeChange.

It is essential that changes to the IR are reported correctly,
since for example ReassociatePass::run() will indicate that all
analyses are preserved otherwise.
And the CGPassManager determines if the CallGraph is up-to-date
based on status from InstructionCombiningPass::runOnFunction().

Reviewers: craig.topper, rnk, davide

Reviewed By: rnk, davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D34616

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306368 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 05:32:13 +00:00
Hiroshi Inoue
1d9383cd84 [PowerPC] set optimization level in SelectionDAGISel
PowerPC backend does not pass the current optimization level to SelectionDAGISel and so SelectionDAGISel works with the default optimization level regardless of the current optimization level.
This patch makes the PowerPC backend set the optimization level correctly.

Differential Revision: https://reviews.llvm.org/D34615



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306367 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 04:52:17 +00:00
Mandeep Singh Grang
64cca8fa27 [COFF, ARM64] Fix typo in COFF ARM64 Relocation Type
Summary:
Fixed IMAGE_REL_ARM64_PAGEBASE_REL2 ==> IMAGE_REL_ARM64_PAGEBASE_REL21
Refer: http://www.microsoft.com/whdc/system/platform/firmware/PECOFF.mspx

Reviewers: zturner, rnk, ruiu

Reviewed By: ruiu

Subscribers: aemerson, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D34659

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306366 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 04:51:44 +00:00
Craig Topper
6309a52c0b [InstCombine] Add test cases demonstrating that we don't optmize select+cmp+cttz/ctlz when the bitwidth is larger than 64 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306365 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 04:50:47 +00:00
Leslie Zhai
2a1334dd59 [AVR] Migrate to new MCAsmBackend applyFixup and processFixupValue
Reviewers: rafael, dylanmckay, jroelofs, meadori

Reviewed By: rafael, meadori

Subscribers: meadori, llvm-commits

Differential Revision: https://reviews.llvm.org/D34551


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306359 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 03:29:27 +00:00
Chandler Carruth
156cc49e50 [SROA] Further test cleanup and add a test for the actual propagation of
the nonnull attribute distinct from rewriting it into an assume.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306358 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 03:08:45 +00:00
Davide Italiano
8ff688d055 [CFLAA] Move FunctionHandle to llvm::cflaa.
Also, while here, remove an unneeded `using namespace llvm`.
Thanks to George for the suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306355 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 02:43:00 +00:00
Davide Italiano
257136b174 [CFLAA] Move a common function to the header to reduce duplication.
Differential Revision:  https://reviews.llvm.org/D34660

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306354 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 02:25:06 +00:00
Chandler Carruth
477bd758b4 [SROA] Clean up a test case a bit prior to adding more testing for
nonnull as part of fixing PR32902.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306353 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 02:23:15 +00:00
Matthias Braun
ea254cbf8f ScheduleDAGInstrs: Fix fixupKills() adding too many kill flags.
Remove invalid shortcut in fixupKills(): A register needs to be marked
live even when we are not adding a kill flag. This is because a
partially live register must not get a kill flags, but it still needs to
be fully marked live when walking backwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306352 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 00:58:48 +00:00
Davide Italiano
2ba26728be [CFLAA] Use raw pointers instead of Optional<Pointer>. NFC.
Using Optional<> here doesn't seem to be terribly valuable, but
this is not the main point of this change. The change enables
us to merge the (now) two identical copies of parentFunctionOfValue()
that Steensgaard's and Andersens' provide.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306351 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-27 00:33:37 +00:00
Davide Italiano
4d73d7ad46 [CFLAA] Change FunctionHandle to be common to Steensgaard's and Andersens'
Differential Revision:  https://reviews.llvm.org/D34638

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306348 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 23:59:14 +00:00
Wolfgang Pieb
ffee4824e9 DAGCombine: Make sure we only eliminate trunc/extend when the scales of truncation and extension match.
This fixes PR33368.

Reviewer: rksimon

Differential Revision:  https://reviews.llvm.org/D34069



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306345 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 23:05:51 +00:00
Dehao Chen
74c2abe3c6 revert r306336 for breaking ppc test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306344 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 23:05:35 +00:00
Eugene Zelenko
ea42b4f0bd [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306341 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 22:44:03 +00:00
Vedant Kumar
1c3c1bee72 [Coverage] Improve readability by using a struct. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306340 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 22:33:06 +00:00
Ayal Zaks
bfc8711de9 reverting 306331.
Causes TBAA metadata to be generates on reverse shuffles, investigating.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306338 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 22:26:54 +00:00
Sanjay Patel
a31e3ee304 [x86] add tests for missing sbb transforms; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306337 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 22:20:07 +00:00
Dehao Chen
fd167cf907 Enable vectorizer-maximize-bandwidth by default.
Summary:
vectorizer-maximize-bandwidth is generally useful in terms of performance. I've tested the impact of changing this to default on speccpu benchmarks on sandybridge machines. The result shows non-negative impact:

spec/2006/fp/C++/444.namd                 26.84  -0.31%
spec/2006/fp/C++/447.dealII               46.19  +0.89%
spec/2006/fp/C++/450.soplex               42.92  -0.44%
spec/2006/fp/C++/453.povray               38.57  -2.25%
spec/2006/fp/C/433.milc                   24.54  -0.76%
spec/2006/fp/C/470.lbm                    41.08  +0.26%
spec/2006/fp/C/482.sphinx3                47.58  -0.99%
spec/2006/int/C++/471.omnetpp             22.06  +1.87%
spec/2006/int/C++/473.astar               22.65  -0.12%
spec/2006/int/C++/483.xalancbmk           33.69  +4.97%
spec/2006/int/C/400.perlbench             33.43  +1.70%
spec/2006/int/C/401.bzip2                 23.02  -0.19%
spec/2006/int/C/403.gcc                   32.57  -0.43%
spec/2006/int/C/429.mcf                   40.35  +0.27%
spec/2006/int/C/445.gobmk                 26.96  +0.06%
spec/2006/int/C/456.hmmer                  24.4  +0.19%
spec/2006/int/C/458.sjeng                 27.91  -0.08%
spec/2006/int/C/462.libquantum            57.47  -0.20%
spec/2006/int/C/464.h264ref               46.52  +1.35%

geometric mean                                   +0.29%

The regression on 453.povray seems real, but is due to secondary effects as all hot functions are bit-identical with and without the flag.

I started this patch to consult upstream opinions on this. It will be greatly appreciated if the community can help test the performance impact of this change on other architectures so that we can decided if this should be target-dependent.

Reviewers: hfinkel, mkuper, davidxl, chandlerc

Reviewed By: chandlerc

Subscribers: rengolin, sanjoy, javed.absar, bjope, dorit, magabari, RKSimon, llvm-commits, mzolotukhin

Differential Revision: https://reviews.llvm.org/D33341

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306336 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 21:41:09 +00:00
Dehao Chen
e43cb60ea4 Fix the bug when handling shufflevector for aarch64.
Summary: This Fixes https://bugs.llvm.org/show_bug.cgi?id=33600

Reviewers: mssimpso, davidxl, Carrot

Reviewed By: mssimpso

Subscribers: aemerson, rengolin, sanjoy, javed.absar, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D34641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306334 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 21:33:51 +00:00
Matt Arsenault
ab5d97fb87 RenameIndependentSubregs: Fix iterator problem
Fixes bug 33597.

Use of substituteRegister in the tied operand case messes
up the register use iterator, causing some uses to be left
unprocessed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306333 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 21:33:36 +00:00
Vassil Vassilev
fff93248d0 Add missing forward declaration.
This should fix our modules builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306332 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 21:11:29 +00:00
Ayal Zaks
faf416b5ae [LV] Changing the interface of ValueMap, NFC.
Instead of providing access to the internal MapStorage holding all Values
associated with a given Key, used for setting or resetting them all together,
ValueMap keeps its MapStorage internal; its new interface allows getting,
setting or resetting a single Value, per part or per part-and-lane.
Follows the discussion in https://reviews.llvm.org/D32871.

Differential Revision: https://reviews.llvm.org/D34473


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306331 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 21:03:51 +00:00
Sam Clegg
3a8fe655a5 [WebAssembly] Add more support for weak symbols
Add weak symbol tests to MC
Add symbol flags to output of `llvm-readobj -t`.

Differential Revision: https://reviews.llvm.org/D34635

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306330 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 21:01:39 +00:00
Tim Northover
05321d30b5 AArch64: legalize G_EXTRACT operations.
This is the dual problem to legalizing G_INSERTs so most of the code and
testing was cribbed from there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306328 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 20:34:13 +00:00
Paul Robinson
d2381bc76f [DWARF] NFC: Give DwarfFormat a 1-byte base type.
In particular this reduces DWARFFormParams from 64 to 32 bits; pass it
around by value.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306324 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 19:52:32 +00:00
Tim Northover
6649090b22 AArch64: remove all kill flags when extending register liveness.
When we forward a stored value to a load and eliminate it entirely we need to
make sure the liveness of the register is maintained all the way to its use.
Previously we only cleared liveness on the store doing the forwarding, but
there could be other killing uses in between.

We already do the right thing when the load has to be converted into something
else, it was just this one path that skipped it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306318 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 18:49:25 +00:00
Paul Robinson
fd770ea497 [DWARF] NFC: Collect info used by DWARFFormValue into a helper.
Some forms have sizes that depend on the DWARF version, DWARF format
(32/64-bit), or the size of an address.  Collect these into a struct
to simplify passing them around.  Require callers to provide one when
they query a form's size.

Differential Revision: http://reviews.llvm.org/D34570


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306315 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 18:43:01 +00:00
Simon Pilgrim
b988cd6c7f [X86][SSE] Check SSE2/SSE3 codegen tests on i686 and x86_64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306314 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 18:20:46 +00:00
Wei Mi
71d7c09ce8 [GVN] Recommit the patch "Add phi-translate support in scalarpre".
The recommit fixes three bugs: The first one is to use CurrentBlock instead of
PREInstr's Parent as param of performScalarPREInsertion because the Parent
of a clone instruction may be uninitialized. The second one is stop PRE when
CurrentBlock to its predecessor is a backedge and an operand of CurInst is
defined inside of CurrentBlock. The same value defined inside of loop in last
iteration can not be regarded as available. The third one is an out-of-bound
array access in a flipped if guard.

Right now scalarpre doesn't have phi-translate support, so it will miss some
simple pre opportunities. Like the following testcase, current scalarpre cannot
recognize the last "a * b" is fully redundent because a and b used by the last
"a * b" expr are both defined by phis.

long a[100], b[100], g1, g2, g3;
__attribute__((pure)) long goo();

void foo(long a, long b, long c, long d) {

  g1 = a * b;
  if (__builtin_expect(g2 > 3, 0)) {
    a = c;
    b = d;
    g2 = a * b;
  }
  g3 = a * b;      // fully redundant.

}

The patch adds phi-translate support in scalarpre. This is only a temporary
solution before the newpre based on newgvn is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306313 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 18:16:10 +00:00
Matt Arsenault
8e828b87b2 AMDGPU: Setup SP/FP in callee function prolog/epilog
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306312 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 17:53:59 +00:00
Eric Beckmann
69e4d36881 Replace trivial use of external rc.exe by writing our own .res file.
This patch removes the dependency on the external rc.exe tool by writing
a simple .res file using our own library. In this patch I also added an
explicit definition for the .res file magic.  Furthermore, I added a
unittest for embeded manifests and fixed a bug exposed by the test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306311 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 17:43:30 +00:00
Zachary Turner
7226719a52 [llvm-pdbutil] Add a mode to bytes for dumping split debug chunks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306309 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 17:22:36 +00:00
Brian Gesiak
8ae15db2a4 [opt-viewer] Python 3 support in opt-stats.py
Summary: Minor changes that allow opt-stats.py to support both Python 2 and 3.

Reviewers: anemet, davidxl

Reviewed By: anemet

Subscribers: llvm-commits, fhahn

Differential Revision: https://reviews.llvm.org/D34564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306306 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 16:51:24 +00:00
Ulrich Weigand
18f8cae766 [SystemZ] Fix missing emergency spill slot corner case
We sometimes need emergency spill slots for the register scavenger.
This may be the case when code needs to access a stack slot that
has an offset of 4096 or more relative to the stack pointer.

To make that determination, processFunctionBeforeFrameFinalized
currently simply checks the total stack frame size of the current
function.  But this is not enough, since code may need to access
stack slots in the caller's stack frame as well, in particular
incoming arguments stored on the stack.

This commit fixes the problem by taking argument slots into account.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306305 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 16:50:32 +00:00
Simon Pilgrim
575411ebf8 [X86][SSE] Add combine tests for PMULDQ/PMULUDQ
Found several missed optimizations while investigating replacing _mm_mul_epi32/_mm_mul_epu32 with generic implementations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306302 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 16:22:52 +00:00
Marina Yatsina
2db1a71f59 [inline asm] dot operator while using imm generates wrong ir + asm - llvm part
Inline asm dot operator while using imm generates wrong ir and asm

This also fixes bugzilla 32987:
https://bugs.llvm.org//show_bug.cgi?id=32987

The clang part of the review that contains the test can be found here:
https://reviews.llvm.org/D33040

commit on behald of zizhar

Differential Revision:
https://reviews.llvm.org/D33039



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306300 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 16:03:42 +00:00
Ahmed Bougacha
699f4c431d [X86][AVX-512] Don't raise inexact in ceil, floor, round, trunc.
The non-AVX-512 behavior was changed in r248266 to match N1778
(C bindings for IEEE-754 (2008)), which defined the four functions
to not raise the inexact exception ("rint" is still defined as raising
it).

Update the AVX-512 lowering of these functions to match that: it should
not be different.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306299 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 16:00:24 +00:00
Tom Stellard
8d3ca7cfeb AMDGPU/GlobalISel: Mark 32-bit G_SHL as legal
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D34589

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306298 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 15:56:52 +00:00
Simon Pilgrim
d71e04af3a [X86] Add test case for PR15981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306296 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-26 15:53:11 +00:00