38142 Commits

Author SHA1 Message Date
Jan Vesely
7417b1b88a AMDGPU: Add support for MCExpr to instruction printer
Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269477 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 20:39:24 +00:00
Jan Vesely
d32e2de242 AMDGPU/R600: Use machine operands instead of ints to track literals
This will be used for global addresses

Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19789

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269476 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 20:39:22 +00:00
Jan Vesely
06fcf3416b AMDGPU/R600: There are other uses for ALU_LITERAL besides Imm
This will be used for GV

Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19788

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269475 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 20:39:20 +00:00
Jan Vesely
03bb0f57a8 AMDGPU: Make CONST_DATA_PTR available to R600
Rename to AMDGPUconstdata_ptr

Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19786

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269474 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 20:39:18 +00:00
Jan Vesely
a8d19bb081 AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2)
Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269473 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 20:39:16 +00:00
Tim Northover
6e490efa61 ARM: use callee-saved list in the order they're actually saved.
When setting the frame pointer, the offset from SP is calculated based on the
stack slot it gets allocated, but this slot is in turn based on the order of
the CSR list so that list should match the order we actually save the registers
in. Mostly it did, but in the edge-case of MachO AAPCS targets it was wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269459 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 19:16:14 +00:00
Krzysztof Parzyszek
d1ae63365b [Hexagon] Remove dead nodes from SelectionDAG to avoid cycles
Recent changes to the instruction selection code exposed a problem where
a dead node was not removed on time. This node had both input and output
chains, which lead to an apparent cycle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269458 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 18:48:15 +00:00
Konstantin Zhuravlyov
a3570477c9 [AMDGPU] Update nop insertion for debugger usage
- Insert one nop for each high level statement instead of two
- Do not insert nop before prologue

Differential Revision: http://reviews.llvm.org/D20215


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269452 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 18:21:28 +00:00
Paul Osmialowski
0b30fc6010 add support for -print-imm-hex for AArch64
Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro,
but not all of them.

Implementation contains following rules:

- floating point immediates are always printed as decimal
- signed integer immediates are printed depends on flag settings
  (for negative values 'formatImm' macro prints the value as i.e -0x01
  which may be convenient when imm is an address or offset)
- logical immediates are always printed as hex
- the 64-bit immediate for advSIMD, encoded in "a🅱️c:d:e:f:g:h" is always printed as hex
- the 64-bit immedaite in exception generation instructions like:
  brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex
- the rest of immediates is printed depends on availability
  of -print-imm-hex

Signed-off-by: Maciej Gabka <maciej.gabka@arm.com>
Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com>

Differential Revision: http://reviews.llvm.org/D16929

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269446 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 18:00:09 +00:00
Krzysztof Parzyszek
68320523d7 [scan-build] fix dead store warnings emitted on LLVM Hexagon code base
Patch by Apelete Seketeli.

Differential Revision: http://reviews.llvm.org/D19900


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269415 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 13:13:59 +00:00
Krzysztof Parzyszek
fca753e55b [MIB] Create a helper function getRegState to extract all register flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269414 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 13:01:19 +00:00
Amjad Aboud
c0cc51c8de Assure calling "cld" instruction in prologue of X86 interrupt handler function.
Differential Revision: http://reviews.llvm.org/D18725


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269413 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 12:46:57 +00:00
Daniel Sanders
ce7190c29e [mips][ias] Work around yet another incorrect microMIPS relocation evaluation exposed by r268900.
It's not entirely clear why R_MICROMIPS_(GOT|HI16|LO16) are evaluated
incorrectly in a small number of the LNT tests at this point. However, it's not
related to the STO_MIPS_MICROMIPS issue.

At this point all the microMIPS-related changes of r268900 have been reverted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269410 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 12:07:14 +00:00
Hrvoje Varga
2d6c428cea [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions
Differential Revision: http://reviews.llvm.org/D14117


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269408 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 11:32:53 +00:00
Justin Bogner
d3d1bf008b SDAG: Clean up a dangling node in SparcISelDAGToDAG::SelectImpl
When we convert to the void Select interface, leaving unreferenced
nodes around won't be allowed anymore.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269396 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 06:37:53 +00:00
Justin Bogner
dd1c5d4daf SDAG: Clean up a dangling node in MipsISelDAGToDAG::SelectImpl
When we convert to the void Select interface, leaving unreferenced
nodes around won't be allowed anymore.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269394 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 06:30:15 +00:00
Justin Bogner
d58331549d SDAG: Implement Select instead of SelectImpl in MSP430DAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
  the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269393 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 06:10:50 +00:00
Matt Arsenault
1e466e511b AMDGPU: Remove verifier check for scc live ins
We only really need this to be true for SIFixSGPRCopies.
I'm not sure there's any way this could happen before that point.

Fixes a case where MachineCSE could introduce a cross block
scc use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269391 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-13 04:15:48 +00:00
Justin Bogner
867b1dadfc SDAG: Implement Select instead of SelectImpl in AArch64DAGToDAGISel
This one has a lot of code churn, but it's all mechanical and
straightforward.

- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
  the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269379 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 23:10:30 +00:00
Justin Bogner
f368c39798 SDAG: Implement Select instead of SelectImpl in LanaiDAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269364 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 21:56:18 +00:00
Justin Bogner
f00111d734 SDAG: Implement Select instead of SelectImpl in HexagonDAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead.
- Where we had already replaced all uses and we returned a node, just
  remove the dead node instead.
- Where we would return null to fall back to another selector, rename
  the method to try* and return a bool for success.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269358 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 21:46:18 +00:00
Justin Bogner
fb5966a02a SDAG: Clean up a dangling node in HexagonISelDAGToDAG::SelectImpl
When we convert to the void Select interface, leaving unreferenced
nodes around won't be allowed anymore.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269355 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 21:24:23 +00:00
Renato Golin
abc00cb813 [ARM] Support and tests for transform of LDR rt, = to MOV
This change implements the transformation in processInstruction() for the
LDR rt, =expression to MOV rt, expression when the expression can be evaluated
and can fit into the immediate field of the MOV or a MVN.

Across the ARM and Thumb instruction sets there are several cases to consider,
each with a different range of representatble constants.

In ARM we have:
 * Modified immediate (All ARM architectures)
 * MOVW (v6t2 and above)

In Thumb we have:
 * Modified immediate (v6t2, v7m and v8m.mainline)
 * MOVW (v6t2, v7m, v8.mainline and v8m.baseline)
 * Narrow Thumb MOV that can be used in an IT block (non flag-setting)

If the immediate fits any of the available alternatives then we make the transformation.

Fixes 25722.

Patch by Peter Smith.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269354 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 21:22:42 +00:00
Renato Golin
44478fede5 [ARM] Delay ARM constant pool creation. NFC.
This change adds a new constant pool kind to ARMOperand. When parsing the
operand for =immediate we create an instance of this operand rather than
creating a constant pool entry and rewriting the operand.

As the new operand kind is only created for ldr rt,= we can make ldr rt,=
an explicit pseudo instruction in ARM, Thumb and Thumb2

The pseudo instruction is expanded in processInstruction(). This creates the
constant pool and transforms the pseudo instruction into a pc-relative ldr to
the constant pool.

There are no functional changes and no modifications needed to existing tests.

Required by the patch that fixes PR25722.

Patch by Peter Smith.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269352 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 21:22:31 +00:00
Justin Bogner
156b5ed92c SDAG: Implement Select instead of SelectImpl in BPFDAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269350 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 21:14:47 +00:00
Justin Bogner
42e9bbeb4c SDAG: Implement Select instead of SelectImpl in AMDGPUDAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
  the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269349 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 21:03:32 +00:00
Justin Bogner
d9641c92d5 SDAG: Clean up dangling nodes in AArch64ISelDAGToDAG::SelectImpl
When we convert to the void Select interface, leaving unreferenced
nodes around won't be allowed anymore.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269345 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 20:54:27 +00:00
Amjad Aboud
22ef2ed5bb Fixed the callee saved registers list for X86 AllRegs calling convention.
32-bit AllRegs:
SSE: xmm0-xmm7
AVX: ymm0-ymm7
AVX512: zmm0-zmm7 + k0-k7

64-bit AllRegs:
SSE: xmm0-xmm15
AVX: ymm0-ymm15
AVX512: zmm0-zmm31 + k0-k7

Differential Revision: http://reviews.llvm.org/D20142


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269337 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 19:58:32 +00:00
Chad Rosier
046f9cb64a [AArch64] Give function a more appropriate name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269335 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 19:51:58 +00:00
Amjad Aboud
72d48093e7 Fixed dwarf X86-32 register mapping for k0-k7 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269333 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 19:49:24 +00:00
Chad Rosier
9d99b756fa [AArch64] Minor refactoring to simplify future patch. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269329 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 19:38:18 +00:00
Krzysztof Parzyszek
d54aa7c3b5 [Hexagon] Expand VSelect pseudo instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269328 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 19:16:02 +00:00
Krzysztof Parzyszek
9c350c822f [Hexagon] Properly handle instruction selection of vsplat intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269312 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 17:21:40 +00:00
Daniel Sanders
100018952c [mips][ias] Fix O32 .cprestore directive when inside .set noat region and offset is in range.
Summary:
This expands on r269179 to fix an additional case that was not covered by our
tests. The assembler temporary is not needed when the .cprestore offset fits
inside a simm16 and it is not an error to use it inside a '.set noat' in this
case.

Reviewers: emaste, seanbruno, sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D20199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269295 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 14:01:50 +00:00
Daniel Sanders
d89f32c83d [mips][ias] Work around incorrect another microMIPS relocation evaluation exposed by r268900
As explained in r269196, microMIPS has a special case that is not correctly
implemented in LLVM. If we have a symbol 'foo' which is equivalent to
'.text+0x10'. The value of an R_MICROMIPS_LO16 relocation using 'foo' is
'foo+0x11' and not 'foo+0x10'. The in-place addend should therefore be 0x11.

This commit reverts a little more of the effect of r268900 by keeping the
symbol when the STO_MIPS_MICROMIPS flag is set for R_MIPS_GPREL32 relocations.
This fixes SingleSource/UnitTests/2003-08-11-VaListArg, and
SingleSource/UnitTests/2003-05-07-VarArgs for microMIPS.

I believe there are additional relocations that have the same issue (e.g.
R_MIPS_64, and R_MIPS_GPREL16) but for now I'm focusing on restoring our
internal buildbots back to the green state we had in r268899.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269294 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 13:39:13 +00:00
Chad Rosier
443898c3e6 [AArch64] Remove command-line option use for testing.
The EXTR combine has been in tree for over 2 years without complain, so go ahead
and remove the option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269292 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 13:27:24 +00:00
Hrvoje Varga
6c8d6522ab Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"
This reverts commit r269176 as it caused test-suite failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269287 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 12:46:06 +00:00
Renato Golin
5c224e802b [scan-build] fix warnings emitted on LLVM ARM code base
Fix "Logic error" warnings of the type "Called C++ object pointer is
null" reported by Clang Static Analyzer.

Patch by Apelete Seketeli.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269285 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 12:33:33 +00:00
Daniel Sanders
b58361c4a0 [mips][ias] Correct ELF eflags when Octeon is the target.
Reviewers: sdardis

Subscribers: petarj, mpf, dsanders, spetrovic, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D18899

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269283 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 11:31:19 +00:00
Daniel Sanders
f6248f5f78 [mips][ias] Handle N64 compound relocations and R_MIPS_SUB in needsRelocateWithSymbol()
Summary:
This eliminates the default case for N64 that was left out of r269047.

The change to R_MIPS_SUB is needed in this patch to make this testable since
%lo(%neg(%gp_rel(foo))) and %hi(%neg(%gp_rel(foo))) remain the only ways to get
a compound relocation from the assembler.

Reviewers: sdardis, rafael

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269280 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 10:55:00 +00:00
Dan Gohman
ca8feb05bb [WebAssembly] Fast-isel support for calls, arguments, and selects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269273 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 04:19:09 +00:00
Hal Finkel
db6adcba1e [PowerPC] Fix a DAG replacement bug in PPCTargetLowering::DAGCombineExtBoolTrunc
While promoting nodes in PPCTargetLowering::DAGCombineExtBoolTrunc, it is
possible for one of the nodes to be replaced by another. To make sure we do not
visit the deleted nodes, and to make sure we visit the replacement nodes, use a
list of HandleSDNodes to track the to-be-promoted nodes during the promotion
process.

The same fix has been applied to the analogous code in
PPCTargetLowering::DAGCombineTruncBoolExt.

Fixes PR26985.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269272 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 04:00:56 +00:00
Matt Arsenault
b381ae290d AMDGPU: Fix getIntegerAttribute type and error message
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269268 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 02:45:18 +00:00
Matt Arsenault
8adf4ebcf3 AMDGPU: Fix breaking IR on instructions with multiple pointer operands
The promote alloca pass would attempt to promote an alloca with
a select, icmp, or phi user, even though the other operand was
from a non-promotable source, producing a select on two different
pointer types.

Only do this if we know that both operands derive from the same
alloca. In the future we should be able to relax this to an alloca
which will also be promoted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269265 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 01:58:58 +00:00
Chad Rosier
dd7a9752c2 [AArch64] Add support for unscaled narrow stores in getUsefulBitsForUse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269263 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 01:42:01 +00:00
Chad Rosier
f600385f77 [AArch64] Remove floating-point narrow stores from getUsefulBitsForUse.
While not impossible, it's unlikely we'd be performing bitwise operations on FP
values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269260 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 01:04:15 +00:00
Justin Bogner
830e803141 SDAG: Implement Select instead of SelectImpl in ARMDAGToDAGISel
This is a large change, but it's pretty mechanical:
- Where we were returning a node before, call ReplaceNode instead.
- Where we would return null to fall back to another selector, rename
  the method to try* and return a bool for success.
- Where we were calling SelectNodeTo, just return afterwards.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269258 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 00:31:09 +00:00
Justin Bogner
0d359b1e28 SDAG: Clean up dangling nodes in ARMISelDAGToDAG::SelectImpl
When we convert to the void Select interface, leaving unreferenced
nodes around won't be allowed anymore.

Part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269256 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-12 00:20:19 +00:00
Justin Bogner
9ad2a7e5c0 SDAG: Use ReplaceNode here, not ReplaceUses
This was a typo in an earlier commit - there's no point in keeping the
old node around here.

Noticed by Meador Inge. Thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269245 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-11 22:21:50 +00:00
Justin Bogner
e819b3304b SDAG: Add a helper to replace and remove a node during ISel
It's very common to want to replace a node and then remove it since
it's dead, especially as we port backends from the SDNode *Select API
to the void Select one. This helper makes this sequence a bit less
verbose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269236 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-11 21:13:17 +00:00