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Author SHA1 Message Date
Dylan Noblesmith
ccc9a59614 VMCore: add assert for miscompile 
See PR11652. Trying to add this assert to
setSubclassData() itself actually prevented
the miscompile entirely, so it has to be here.

This makes the source of the bug more obvious
than the other asserts triggering later on did.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147390 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-31 13:58:58 +00:00
Bruno Cardoso Lopes
ce8524c016 Cleanup Mips code and rename some variables. Patch by Jack Carter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147383 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 21:09:41 +00:00
Bruno Cardoso Lopes
3aa035fa0c Improve Mips JIT. 
Implement encoder methods getJumpTargetOpValue and getBranchTargetOpValue
for jmptarget and brtarget Mips tablegen operand types in the code emitter
for old-style JIT. Rename the pc relative relocation for branches - new
name is Mips::reloc_mips_pc16.

Patch by Sasa Stankovic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147382 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 21:04:30 +00:00
Nick Lewycky
db186c4c83 Remove extraneous ".get()->" which is just "->". No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147379 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 19:17:23 +00:00
Craig Topper
7ba2725f5d Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing from Bulldozer CPU types since it would enable AVX code generation implicitly. Also make SSE4A imply SSE3. Without some level of SSE implied, XMM registers wouldn't be legal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147369 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 07:16:00 +00:00
Craig Topper
06f554d06a Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 06:23:39 +00:00
Craig Topper
e6a3a2990e Add FMA4 instructions to disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 05:20:36 +00:00
Craig Topper
5d1a38cbfa Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 04:48:54 +00:00
Craig Topper
4d5c4423b9 Combine FMA4 SS/SD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147365 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:33:59 +00:00
Craig Topper
ca28590d8b Combine FMA4 PS/PD patterns with the instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147364 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 03:17:15 +00:00
Craig Topper
2e9ed29449 Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to force alignment on these instructions. Add a couple testcases for memory forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147361 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 02:18:36 +00:00
Craig Topper
57d4b3315f Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 01:49:53 +00:00
Hal Finkel
2e95afa04c Cleanup stack/frame register define/kill states. This fixes two bugs: 
1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test).

2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-30 00:34:00 +00:00
Rafael Espindola
ed23bdb65f Implement cfi_restore. Patch by Brian Anderson! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 21:43:03 +00:00
Rafael Espindola
c25680f728 Rename Remember and Restore to RememberState and RestoreState for consistency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147354 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 21:09:08 +00:00
Craig Topper
1604ccfc01 Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:43:40 +00:00
Rafael Espindola
6f0b181bc7 Implement .cfi_escape. Patch by Brian Anderson! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:24:47 +00:00
Craig Topper
19f18be449 Expose FMA3 instructions to the disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 20:03:14 +00:00
Craig Topper
c38fff4277 Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types aren't valid unless AVX is enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147349 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 19:46:19 +00:00
Craig Topper
5ebee4494b Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 19:25:56 +00:00
Craig Topper
8493e39014 Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A in r147339. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:47:31 +00:00
Craig Topper
b75f5f7d5d Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:08:36 +00:00
Craig Topper
78be212d1b Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 18:00:08 +00:00
Craig Topper
d65c7da5b0 Remove the separate explicit AES instruction patterns. They are equivalent to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 17:41:56 +00:00
Craig Topper
d4d3513d37 Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 15:51:45 +00:00
Craig Topper
19ec2a9db1 Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL for v16i16 and v32i8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 03:34:54 +00:00
Craig Topper
d62c16e535 Remove some elses after returns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 03:20:51 +00:00
Craig Topper
3224e6b60a Remove trailing spaces. Fix an assert to use && instead of || before string. Add same assert on similar code path. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147335 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 03:09:33 +00:00
Rafael Espindola
3a023d3180 Fix grammar error noticed by Duncan. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147333 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-29 02:15:06 +00:00
Nick Lewycky
b48a18903a Change CaptureTracking to pass a Use* instead of a Value* when a value is 
captured. This allows the tracker to look at the specific use, which may be
especially interesting for function calls.

Use this to fix 'nocapture' deduction in FunctionAttrs. The existing one does
not iterate until a fixpoint and does not guarantee that it produces the same
result regardless of iteration order. The new implementation builds up a graph
of how arguments are passed from function to function, and uses a bottom-up walk
on the argument-SCCs to assign nocapture. This gets us nocapture more often, and
does so rather efficiently and independent of iteration order.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147327 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 23:24:21 +00:00
Eli Friedman
da813f4209 Fix type-checking for load transformation which is not legal on floating-point types. PR11674. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 21:24:44 +00:00
Bob Wilson
eaf0608891 Update OCaml bindings for the new half float type. 
Patch by Jonathan Ragan-Kelley!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147314 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 18:51:08 +00:00
Rafael Espindola
97fb69b2ef Add support for mipsel in configure. Fixes PR11669. Patch by Sylvestre Ledru. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147312 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 17:08:00 +00:00
Nadav Rotem
6059b83695 PR11662. 
Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147309 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 13:08:20 +00:00
Elena Demikhovsky
021c0a2ee7 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. 
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 08:14:01 +00:00
Nick Lewycky
8da7ddf2d2 Demystify this comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147307 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 06:57:32 +00:00
Rafael Espindola
99f9a20ba3 PR11642 has been fixed, enable -fvisibility-inlines-hidden everywhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 21:37:11 +00:00
Benjamin Kramer
c894b02ae0 Switch StringMap from an array of structures to a structure of arrays. 
- -25% memory usage of the main table on x86_64 (was wasted in struct padding).
- no significant performance change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147294 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 20:35:07 +00:00
Nick Lewycky
91968489d7 Use false not zero, as a bool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 18:27:22 +00:00
Nick Lewycky
a6b21ea4ba Turn cos(-x) into cos(x). Patch by Alexander Malyshev! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147291 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 18:25:50 +00:00
Benjamin Kramer
27baab62e7 Clean up some Release build warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 11:41:05 +00:00
Craig Topper
3738ccd7eb Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 06:27:23 +00:00
Nick Lewycky
06cc66f65a Teach simplifycfg to recompute branch weights when merging some branches, and 
to discard weights when appropriate. Still more to do (and a new TODO), but
it's a start!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 04:31:52 +00:00
Nick Lewycky
da32cc6176 Using Inst->setMetadata(..., NULL) should be safe to remove metadata even when 
there is non of that type to remove. This fixes a crasher in the particular
case where the instruction has metadata but no metadata storage in the context
(this is only possible if the instruction has !dbg but no other metadata info).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-27 01:17:40 +00:00
Rafael Espindola
125ef76934 Fix warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-26 23:12:42 +00:00
Eli Friedman
d6e2560e7a Make sure DAGCombiner doesn't introduce multiple loads from the same memory location. PR10747, part 2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-26 22:49:32 +00:00
Nick Lewycky
c9a1aed7fe Update the branch weight metadata when reversing the order of a branch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147280 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-26 20:54:14 +00:00
Nick Lewycky
9d52310222 Sort includes, canonicalize whitespace, fix typos. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147279 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-26 20:37:40 +00:00
Nadav Rotem
859c645310 Update the LangRef documentation: the codegen does support this instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-25 21:32:35 +00:00
Nadav Rotem
fbb6f593c2 Fix a typo in the widening of vectors in PromoteIntRes. Patch by Shemer Anat. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-25 20:01:38 +00:00