We didn't check for the necessary preconditions before folding a
mask/shift into a single mask.
This fixes PR24516.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245544 91177308-0d34-0410-b5e6-96231b3b80d8
Usually DSE is not supposed to remove lifetime intrinsics, but it's
actually ok to remove them for dead objects in terminating blocks,
because they convey no extra information there. Until we hit a lifetime
start that cannot be removed, that is. Because from that point on the
lifetime intrinsics become interesting again, e.g. for stack coloring.
Reviewers: reames
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11710
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245542 91177308-0d34-0410-b5e6-96231b3b80d8
analyses into LLVM's Analysis library rather than having them in
a Transforms library.
This is motivated by the need to have the core AliasAnalysis
infrastructure be aware of the ObjCARCAliasAnalysis. However, it also
seems like a nice and clean separation. Everything was very easy to move
and this doesn't create much clutter in the analysis library IMO.
Differential Revision: http://reviews.llvm.org/D12133
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245541 91177308-0d34-0410-b5e6-96231b3b80d8
XVCMPEQDP is used for VSX v2f64 equality comparisons, but the value type needs
to be v2i64 (as that's the corresponding SETCC type).
Fixes PR24225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245535 91177308-0d34-0410-b5e6-96231b3b80d8
This DAGCombine was creating custom SDAG nodes with an illegal ppc_fp128
operand type because it was triggering on f64/f32 int2fp(fp2int(ppc_fp128 x)),
but shouldn't (it should only apply to f32/f64 types). The result was a crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245530 91177308-0d34-0410-b5e6-96231b3b80d8
This commit modifies the serialization syntax so that the global IR values in
machine memory operands use the global value '@<name>' syntax instead of the
current '%ir.<name>' syntax.
The unnamed global IR values are handled by this commit as well, as the
existing global value parsing method can parse the unnamed globals already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245527 91177308-0d34-0410-b5e6-96231b3b80d8
The global IR values in machine memory operands should use the global value
'@<name>' syntax instead of the current '%ir.<name>' syntax.
However, the global value call entry pseudo source values use the global value
syntax already. Therefore, the syntax for the call entry pseudo source values
has to be changed so that the global values and call entry global value PSVs
can be parsed without ambiguities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245526 91177308-0d34-0410-b5e6-96231b3b80d8
Machine memory operands can contain pointer values that are constants, and
the 'getLocalSlot' method requires non-constant values.
The constant pointer values will have to be serialized in a different patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245523 91177308-0d34-0410-b5e6-96231b3b80d8
This is something like nullopt in std::experimental::optional. Optional
could already be constructed from None, so this seems like an obvious
extension from there.
I have a use in a future patch for Clang, though it may not go that
way/end up used - so this seemed worth committing now regardless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245518 91177308-0d34-0410-b5e6-96231b3b80d8
We still need to add constant folding of vector comparisons to fold the tests for targets that don't support the respective min/max nodes
I needed to update 2011-12-06-AVXVectorExtractCombine to load a vector instead of using a constant vector to prevent it folding
Differential Revision: http://reviews.llvm.org/D12118
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245503 91177308-0d34-0410-b5e6-96231b3b80d8
We are already falling back to SelectionDAG when encountering an shift with UB.
This adds the same checks for shifts with UB that get folded into arithmetic or
logical operations.
This fixes rdar://problem/22345295.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245499 91177308-0d34-0410-b5e6-96231b3b80d8
We don't do a great job with >= 0 comparisons against zero when the
result is used as an i8.
Given something like:
void f(long long LL, bool *B) {
*B = LL >= 0;
}
We used to generate:
shrq $63, %rdi
xorb $1, %dil
movb %dil, (%rsi)
Now we generate:
testq %rdi, %rdi
setns (%rsi)
Differential Revision: http://reviews.llvm.org/D12136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245498 91177308-0d34-0410-b5e6-96231b3b80d8
Previously WebAssembly's datalayout string had -v128:8:128. This had been an
attempt to declare a certain level of support for unaligned SIMD accesses.
However, clang makes its own determinations for SIMD alignment that are
independent of the datalayout string, so this wasn't actually meaningful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245494 91177308-0d34-0410-b5e6-96231b3b80d8
Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at most two distinct vectors the same size as the result, attempt to turn this into a legal shuffle.
Differential Revision: http://reviews.llvm.org/D12125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245490 91177308-0d34-0410-b5e6-96231b3b80d8
Besides storing the operand's source range, this structure now stores other
attributes as well, so the name should reflect this fact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245483 91177308-0d34-0410-b5e6-96231b3b80d8
This commit serializes the machine instruction's register operand ties.
The ties are printed out only when the instructon has register ties that are
different from the ties that are specified in the instruction's description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245482 91177308-0d34-0410-b5e6-96231b3b80d8
This revision has introduced an issue that only affects bootstrapped compiler
when it is printing the ASM. I am working on resolving the issue, but in the
meantime, I'm disabling the legalization of scalar_to_vector operation for v2i64
and the associated testing until I can get this fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245481 91177308-0d34-0410-b5e6-96231b3b80d8
The defined registers are already serialized - they are represented by placing
them before the '=' in a machine instruction. However, certain instructions like
INLINEASM can have defined register operands after the '=', so this commit
introduces the 'def' register flag for such operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245480 91177308-0d34-0410-b5e6-96231b3b80d8
Reintroduce r245442. Remove an overly conservative assertion introduced
in r245442. We could replace the assertion to use `shareSameRegisterFile`
instead, but in that point in `insertPHI` we already lost the original
Def subreg to check against. So drop the assertion completely.
Original commit message:
- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI
instructions.
- Add findNextSourceAndRewritePHI method to lookup into multiple sources
returnted by the ValueTracker and rewrite PHIs with new sources.
With these changes we can find more register sources and rewrite more
copies to allow coaslescing of bitcast instructions. Hence, we eliminate
unnecessary VR64 <-> GR64 copies in x86, but it could be extended to
other archs by marking "isBitcast" on target specific instructions. The
x86 example follows:
A:
psllq %mm1, %mm0
movd %mm0, %r9
jmp C
B:
por %mm1, %mm0
movd %mm0, %r9
jmp C
C:
movd %r9, %mm0
pshufw $238, %mm0, %mm0
Becomes:
A:
psllq %mm1, %mm0
jmp C
B:
por %mm1, %mm0
jmp C
C:
pshufw $238, %mm0, %mm0
Differential Revision: http://reviews.llvm.org/D11197
rdar://problem/20404526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245479 91177308-0d34-0410-b5e6-96231b3b80d8
Since r244955, we try to use the short-form ErrorInfo when both
tries failed, and the long-form match failed on a suffix operand.
However, this means we sometimes mix ErrorInfo and MatchResult
(one manifestation of this being PR24498). Instead, restore both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245469 91177308-0d34-0410-b5e6-96231b3b80d8
Rewrite some code to not use a lambda function. The non-lambda code is just
about as clean as the original, and not any longer. The lambda function causes
an internal compiler error in GCC 4.8.0, and it is not worth breaking support
for that compiler over this. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245466 91177308-0d34-0410-b5e6-96231b3b80d8
This reverts commit r245443, as it broke AArch64 test-suite tramp3d
with an assert "Reg && "Null register has no regunits".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245455 91177308-0d34-0410-b5e6-96231b3b80d8
This patch updates the X86 lowering so that the Exception Pointer and Selector
are 64-bit wide only if Subtarget.isTarget64BitLP64.
Patch by João Porto
Reviewers: dschuff, rnk
Differential Revision: http://reviews.llvm.org/D12111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245454 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply r243486.
- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI
instructions.
- Add findNextSourceAndRewritePHI method to lookup into multiple sources
returnted by the ValueTracker and rewrite PHIs with new sources.
With these changes we can find more register sources and rewrite more
copies to allow coaslescing of bitcast instructions. Hence, we eliminate
unnecessary VR64 <-> GR64 copies in x86, but it could be extended to
other archs by marking "isBitcast" on target specific instructions. The
x86 example follows:
A:
psllq %mm1, %mm0
movd %mm0, %r9
jmp C
B:
por %mm1, %mm0
movd %mm0, %r9
jmp C
C:
movd %r9, %mm0
pshufw $238, %mm0, %mm0
Becomes:
A:
psllq %mm1, %mm0
jmp C
B:
por %mm1, %mm0
jmp C
C:
pshufw $238, %mm0, %mm0
Differential Revision: http://reviews.llvm.org/D11197
rdar://problem/20404526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245442 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
The mid-end was generating vector smin/smax/umin/umax nodes, but
we were using vbsl to generatate the code. This adds the vmin/vmax
patterns and a test to check that we are now generating vmin/vmax
instructions.
Reviewers: rengolin, jmolloy
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D12105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245439 91177308-0d34-0410-b5e6-96231b3b80d8
There are some cases where the mul sequence is smaller, but for the most part,
using a div is preferable. This does not apply to vectors, since x86 doesn't
have vector idiv, and a vector mul/shifts sequence ought to be smaller than a
scalarized division.
Differential Revision: http://reviews.llvm.org/D12082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245431 91177308-0d34-0410-b5e6-96231b3b80d8
