Commit Graph

3681 Commits

Author SHA1 Message Date
Joerg Sonnenberger
cadb2a8a32 Add mtpid/mfpid for BookE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214363 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 23:59:11 +00:00
Joerg Sonnenberger
367c5c25e8 Refactor TLBIVAX and add tlbsx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214354 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 22:51:15 +00:00
Joerg Sonnenberger
ee6a05091a Add rfdi and rfmci from the e500/e500mc ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214339 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 21:09:03 +00:00
Joerg Sonnenberger
9e3d58aae1 Add BookE's tlbre, tlbwe and tlbivax instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214332 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 20:44:04 +00:00
Joerg Sonnenberger
a4d6ef15b8 Add BookE's wrtee and wrteei instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214297 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 10:32:51 +00:00
Joerg Sonnenberger
a2d6cb1e55 SPRG 0 to 3 are valid outside BookE, so move them to the normal test
file. Add support for accessing SPRG 4 to 7 on BookE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214295 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 09:24:37 +00:00
Joerg Sonnenberger
f34e598090 Add rfci instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214256 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 23:45:20 +00:00
Joerg Sonnenberger
1bb9c8155a mbar without argument is equivalent to mbar 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214250 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 23:31:27 +00:00
Joerg Sonnenberger
6e48dd6d5b Recognize BookE's mbar instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214244 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 23:16:31 +00:00
Joerg Sonnenberger
2f8f622d18 Fix typo in alias: DSIR -> DSISR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214238 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 22:42:44 +00:00
Joerg Sonnenberger
b9253653c7 Support move to/from segment register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214234 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 22:21:57 +00:00
Joerg Sonnenberger
e31c7fd974 Add a number of aliases for SPR access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214196 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 18:55:43 +00:00
Joerg Sonnenberger
f6689601ee Add rfi instruction. Based on feedback by Ulrich Weigand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214181 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-29 15:49:09 +00:00
Robert Khasanov
281d2bf320 [SKX] Enabling mask logic instructions: encoding, lowering
Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ}

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214081 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-28 13:46:45 +00:00
Saleem Abdulrasool
77b9fc127b ARM: correct handling of features in arch_extension
The subtarget information is the ultimate source of truth for the feature set
that is enabled at this point.  We would previously not propagate the feature
information to the subtarget.  While this worked for the most part (features
would be enabled/disabled as requested), if another operation that changed the
feature bits was encountered (such as a mode switch via a .arm or .thumb
directive), we would end up resetting the behaviour of the architectural
extensions.

Handling this properly requires a slightly more complicated handling.  We need
to check if the feature is now being toggled.  If so, only then do we toggle the
features.  In return, we no longer have to calculate the feature bits ourselves.

The test changes are mostly to the diagnosis, which is now more uniform (a nice
side effect!).  Add an additional test to ensure that we handle this case
properly.

Thanks to Nico Weber for alerting me to this issue!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214057 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-27 19:07:09 +00:00
Lang Hames
b64f8426f2 [X86] Add comments to clarify some non-obvious lines in the stackmap-nops.ll
testcases.

Based on code review from Philip Reames. Thanks Philip!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213923 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-25 04:50:08 +00:00
Lang Hames
b96e833817 [X86] Optimize stackmap shadows on X86.
This patch minimizes the number of nops that must be emitted on X86 to satisfy
stackmap shadow constraints.

To minimize the number of nops inserted, the X86AsmPrinter now records the
size of the most recent stackmap's shadow in the StackMapShadowTracker class,
and tracks the number of instruction bytes emitted since the that stackmap
instruction was encountered. Padding is emitted (if it is required at all)
immediately before the next stackmap/patchpoint instruction, or at the end of
the basic block.

This optimization should reduce code-size and improve performance for people
using the llvm stackmap intrinsic on X86.

<rdar://problem/14959522>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213892 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 20:40:55 +00:00
Saleem Abdulrasool
69280f8844 X86: correct library call setup for Windows itanium
This target is identical to the Windows MSVC (and follows Microsoft ABI for C).
Correct the library call setup for this target.  The same set of library calls
are missing on this environment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 17:46:36 +00:00
Nico Weber
519212bf69 Let the integrated assembler understand .exitm, PR20426.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213876 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 17:08:39 +00:00
Nico Weber
2604a975ba Let the integrated assembler understand .warning, PR20428.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213873 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 16:26:06 +00:00
Tilmann Scheller
d51310e486 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions.
The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213850 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-24 09:55:46 +00:00
Robert Khasanov
8b832c1c39 [SKX] Added missed test files for rev 213757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213780 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-23 18:17:49 +00:00
Robert Khasanov
f47bcb31e0 [SKX] Fix lowercase "error:" in rev 213757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213774 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-23 17:42:13 +00:00
Robert Khasanov
3922da8ae8 [SKX] Enabling mask instructions: encoding, lowering
KMOVB, KMOVW, KMOVD, KMOVQ, KNOTB, KNOTW, KNOTD, KNOTQ

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-23 14:49:42 +00:00
Tilmann Scheller
3b867c9c8e [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB instructions.
The ARM ARM prohibits STRB instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRB instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213750 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-23 13:03:47 +00:00
Tim Northover
8b6257629a AArch64: remove "arm64_be" support in favour of "aarch64_be".
There really is no arm64_be: it was a useful fiction to test big-endian support
while both backends existed in parallel, but now the only platform that uses
the name (iOS) doesn't have a big-endian variant, let alone one called
"arm64_be".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213748 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-23 12:58:11 +00:00
Tilmann Scheller
0f7b2e9db0 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STR instructions.
The ARM ARM prohibits STR instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STR instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213745 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-23 12:38:17 +00:00
Tim Northover
50f2f1434c X86: drop relocations on __eh_frame sections globally.
Without this, we produce non-extern relocations when targeting older OS X
versions that ld64 can't cope with in the particular context of __eh_frame
sections (who'd want generic relocation-processing anyway?).

This means that an updated linker (ld64 from Xcode 3.2.6 or later) may be
needed when targeting such platforms with a modern version of LLVM, but this is
probably the case anyway and a reasonable requirement.

PR20212, rdar://problem/17544795

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213665 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-22 15:47:09 +00:00
Daniel Sanders
6816d66d99 [mips] Add MipsOptionRecord abstraction and use it to implement .reginfo/.MIPS.options
This abstraction allows us to support the various records that can be placed in
the .MIPS.options section in the future. We currently use it to record register
usage information (the ODK_REGINFO record in our ELF64 spec).

Each .MIPS.options record should subclass MipsOptionRecord and provide an
implementation of EmitMipsOptionRecord.

Patch by Matheus Almeida and Toma Tabacu



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 13:30:55 +00:00
Ulrich Weigand
76fcace66e [MC] Pass MCSymbolData to needsRelocateWithSymbol
As discussed in a previous checking to support the .localentry
directive on PowerPC, we need to inspect the actual target symbol
in needsRelocateWithSymbol to make the appropriate decision based
on that symbol's st_other bits.

Currently, needsRelocateWithSymbol does not get the target symbol.
However, it is directly available to its sole caller.  This patch
therefore simply extends the needsRelocateWithSymbol by a new
parameter "const MCSymbolData &SD", passes in the target symbol,
and updates all derived implementations.

In particular, in the PowerPC implementation, this patch removes
the FIXME added by the previous checkin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-20 23:15:06 +00:00
Ulrich Weigand
5ee5fc4c47 [PowerPC] ELFv2 MC support for .localentry directive
A second binutils feature needed to support ELFv2 is the .localentry
directive.  In the ELFv2 ABI, functions may have two entry points:
one for calling the routine locally via "bl", and one for calling the
function via function pointer (either at the source level, or implicitly
via a PLT stub for global calls).  The two entry points share a single
ELF symbol, where the ELF symbol address identifies the global entry
point address, while the local entry point is found by adding a delta
offset to the symbol address.  That offset is encoded into three
platform-specific bits of the ELF symbol st_other field.

The .localentry directive instructs the assembler to set those fields
to encode a particular offset.  This is typically used by a function
prologue sequence like this:

func:
        addis r2, r12, (.TOC.-func)@ha
        addi r2, r2, (.TOC.-func)@l
        .localentry func, .-func

Note that according to the ABI, when calling the global entry point,
r12 must be set to point the global entry point address itself; while
when calling the local entry point, r2 must be set to point to the TOC
base.  The two instructions between the global and local entry point in
the above example translate the first requirement into the second.

This patch implements support in the PowerPC MC streamers to emit the
.localentry directive (both into assembler and ELF object output), as
well as support in the assembler parser to parse that directive.

In addition, there is another change required in MC fixup/relocation
handling to properly deal with relocations targeting function symbols
with two entry points: When the target function is known local, the MC
layer would immediately handle the fixup by inserting the target
address -- this is wrong, since the call may need to go to the local
entry point instead.  The GNU assembler handles this case by *not*
directly resolving fixups targeting functions with two entry points,
but always emits the relocation and relies on the linker to handle
this case correctly.  This patch changes LLVM MC to do the same (this
is done via the processFixupValue routine).

Similarly, there are cases where the assembler would normally emit a
relocation, but "simplify" it to a relocation targeting a *section*
instead of the actual symbol.  For the same reason as above, this
may be wrong when the target symbol has two entry points.  The GNU
assembler again handles this case by not performing this simplification
in that case, but leaving the relocation targeting the full symbol,
which is then resolved by the linker.  This patch changes LLVM MC
to do the same (via the needsRelocateWithSymbol routine).
NOTE: The method used in this patch is overly pessimistic, since the
needsRelocateWithSymbol routine currently does not have access to the
actual target symbol, and thus must always assume that it might have
two entry points.  This will be improved upon by a follow-on patch
that modifies common code to pass the target symbol when calling
needsRelocateWithSymbol.

Reviewed by Hal Finkel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213485 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-20 23:06:03 +00:00
Ulrich Weigand
0d9bcaacd1 [PowerPC] ELFv2 MC support for .abiversion directive
ELFv2 binaries are marked by a bit in the ELF header e_flags field.
A new assembler directive .abiversion can be used to set that flag.
This patch implements support in the PowerPC MC streamers to emit the
.abiversion directive (both into assembler and ELF binary output),
as well as support in the assembler parser to parse the .abiversion
directive.

Reviewed by Hal Finkel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213484 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-20 22:56:57 +00:00
Hal Finkel
d644d17dd4 [PowerPC] 32-bit ELF PIC support
This adds initial support for PPC32 ELF PIC (Position Independent Code; the
-fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
backend.

Patch by Justin Hibbits!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 23:29:49 +00:00
David Peixotto
12f33da20b MC: support different sized constants in constant pools
On AArch64 the pseudo instruction ldr <reg>, =... supports both
32-bit and 64-bit constants. Add support for 64 bit constants for
the pools to support the pseudo instruction fully.

Changes the AArch64 ldr-pseudo tests to use 32-bit registers and
adds tests with 64-bit registers.

Patch by Janne Grunau!

Differential Revision: http://reviews.llvm.org/D4279



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213387 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 16:05:14 +00:00
Adam Nemet
6ae2941874 [X86] AVX512: Add disassembler support for compressed displacement
There are two parts here.  First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.

The second is to use the new encoding types to compute the correct
displacement in the decoder.

Fixes <rdar://problem/17608489>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 17:04:56 +00:00
Saleem Abdulrasool
a056166dc2 MC: fix MCAsmInfo usage for windows-itanium
Windows itanium uses the GNUCOFF assmebly format, not ELF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213274 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 16:27:40 +00:00
Daniel Sanders
8f69856b52 [mips] .reginfo is 8 byte aligned on N32.
Differential Revision: http://reviews.llvm.org/D4540


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213246 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:10:04 +00:00
Daniel Sanders
3da6527068 [mips] Correct ELF e_flags for the N32 ABI when using a mips-* triple rather than a mips64-* triple
Summary:
Generally speaking, mips-* vs mips64-* should not be used to make decisions
about the content or format of the ELF. This should be based on the ABI
and CPU in use. For example, `mips-linux-gnu-clang -mips64r2 -mabi=64`
should produce an ELF64 as should `mips64-linux-gnu-clang -mabi=64`.
Conversely, `mips64-linux-gnu-clang -mabi=n32` should produce an ELF32 as
should `mips-linux-gnu-clang -mips64r2 -mabi=n32`.

This patch fixes the e_flags but leaves the ELF32 vs ELF64 issue for now
since there is no apparent way to base this decision on the ABI and CPU.

Differential Revision: http://reviews.llvm.org/D4539


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213244 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:02:08 +00:00
Daniel Sanders
0a342e9992 [mips] Correct .MIPS.abiflags for -mfpxx on MIPS32r6
Summary:
The cpr1_size field describes the minimum register width to run the program
rather than the size of the registers on the target. MIPS32r6 was acting
as if -mfp64 has been given because it starts off with 64-bit FPU registers.

Differential Revision: http://reviews.llvm.org/D4538


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213243 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 09:57:23 +00:00
Daniel Sanders
4b5e7542df [mips] Fix ELF e_flags related to -mabicalls and -mplt.
Summary:
These options are not implemented yet but we act as if they are always
given.

The integrated assembler is driven by the clang driver so the e_flag test
cases should match the e_flags emitted by GCC+GAS rather than GAS
by itself.

Differential Revision: http://reviews.llvm.org/D4536


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213242 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 09:52:56 +00:00
Tilmann Scheller
2dade438d7 [AArch64] Add negative tests for the SIMD & FP LDP instructions.
LDP is unpredictable if the registers in the pair are identical, these tests check that we don't assemble instructions like that and error out instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213074 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 16:33:24 +00:00
Daniel Sanders
6d6a055c60 [mips] Correct .MIPS.abiflags fp_abi field for -mfpxx and without .module
Summary: Previously all the test cases set it after initialization with '.module fp=xx'.

Differential Revision: http://reviews.llvm.org/D4489


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213071 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 15:31:39 +00:00
Daniel Sanders
52a51e197f Re-commit: [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags
The lld tests will temporarily fail again but Simon Atanasyan will commit a fix for those shortly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212946 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 15:05:51 +00:00
Daniel Sanders
b70b4892a4 Revert: [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags
This commit causes multiple lld tests to fail. Reverting while I investigate the issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212945 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 14:43:45 +00:00
Daniel Sanders
05aee6b5f4 [mips] Correct section alignments and EntrySizes for .bss, .text, .data, .reginfo, .MIPS.options, and .MIPS.abiflags
Summary:
.bss, .text, and .data are at least 16-byte aligned.
.reginfo is 4-byte aligned and has a 24-byte EntrySize.
.MIPS.abiflags has an 24-byte EntrySize.
.MIPS.options is 8-byte aligned and has 1-byte EntrySize.

Using a 1-byte EntrySize for .MIPS.options seems strange because the
records are neither 1-byte long nor fixed-length but this matches the value
that GAS emits.

Differential Revision: http://reviews.llvm.org/D4487


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212939 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 14:02:14 +00:00
Daniel Sanders
e99ebb9b2f [mips] Correct the AFL_FLAGS1_ODDSPREG flag in .MIPS.abiflags when no '.module oddspreg' is used
Differential Revision: http://reviews.llvm.org/D4486


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 10:26:15 +00:00
Simon Atanasyan
b2b56ed1a6 [Mips] Support SHT_MIPS_ABIFLAGS section type flag in the llvm-readobj,
obj2yaml and yaml2obj tools.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212908 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 15:28:54 +00:00
David Majnemer
f803b3d992 MC: Let non-temporary COFF aliases be in symtab
MC was aping a binutils bug where aliases would default their linkage to
private instead of internal.

I've sent a patch to the binutils maintainers and they've recently
applied it to the GNU assembler sources.

This fixes PR20152.

Differential Revision: http://reviews.llvm.org/D4395

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 04:31:19 +00:00
Arnaud A. de Grandmaison
a9af0558b2 [AArch64] Add logical alias instructions to MC AsmParser
This patch teaches the AsmParser to accept some logical+immediate
instructions and convert them as shown:

  bic  Rd, Rn, #imm  ->  and Rd, Rn, #~imm
  bics Rd, Rn, #imm  ->  ands Rd, Rn, #~imm
  orn  Rd, Rn, #imm  ->  orr Rd, Rn, #~imm
  eon  Rd, Rn, #imm  ->  eor Rd, Rn, #~imm

Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers. For example, the bic construct is used by the linux kernel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 15:12:26 +00:00
Daniel Sanders
24a071b8c5 [mips] Add support for -modd-spreg/-mno-odd-spreg
Summary:
When -mno-odd-spreg is in effect, 32-bit floating point values are not
permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit
floating point comparison results from being written to odd registers.

This option has three purposes:
* It allows support for certain MIPS implementations such as loongson-3a that
  do not allow the use of odd registers for single precision arithmetic.
* When using -mfpxx, -mno-odd-spreg is the default and this allows us to
  statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1
  instructions to/from odd registers are guaranteed not to appear for any
  reason. Once this has been established, the user can then re-enable
  -modd-spreg to regain the use of all 32 single-precision registers.
* When using -mfp64 and -mno-odd-spreg together, an O32 extension named
  O32 FP64A is used as the ABI. This is intended to provide almost all
  functionality of an FR=1 processor but can also be executed on a FR=0 core
  with the assistance of a hardware compatibility mode which emulates FR=0
  behaviour on an FR=1 processor.

* Added '.module oddspreg' and '.module nooddspreg' each of which update
  the .MIPS.abiflags section appropriately
* Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller
  doesn't have to remember to do it.
* MipsABIFlags now calculates the flags1 and flags2 member on demand rather
  than trying to maintain them in the same format they will be emitted in.

There is one portion of the -mfp64 and -mno-odd-spreg combination that is not
implemented yet. Moves to/from odd-numbered double-precision registers must not
use mtc1. I will fix this in a follow-up.

Differential Revision: http://reviews.llvm.org/D4383


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 13:38:23 +00:00