Evan Cheng
e163168aab
Code clean up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:42:23 +00:00
Devang Patel
461a646a03
Revert r104165.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:58:28 +00:00
Jakob Stoklund Olesen
d32e735ae6
Add support for partial redefs to the fast register allocator.
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A partial redef now triggers a reload if required. Also don't add
<imp-def,dead> operands for physical superregisters.
Kill flags are still treated as full register kills, and <imp-use,kill> operands
are added for physical superregisters as before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:36:05 +00:00
Devang Patel
f4ccaeaef9
There is no need to maintain InsnsBeginScopeSet separately.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:26:53 +00:00
Jakob Stoklund Olesen
7ebc4d63db
Add MachineInstr::readsVirtualRegister() in preparation for proper handling of
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partial redefines.
We are going to treat a partial redefine of a virtual register as a
read-modify-write:
%reg1024:6 = OP
Unless the register is fully clobbered:
%reg1024:6 = OP, %reg1024<imp-def>
MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:36:22 +00:00
Evan Cheng
211ffa1351
Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:19:50 +00:00
Jakob Stoklund Olesen
3437352887
TwoAddressInstructionPass doesn't really know how to merge live intervals when
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lowering REG_SEQUENCE instructions.
Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:08:00 +00:00
Mikhail Glushenkov
139c9e1f85
llvmc: report an error if a child process segfaults.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104145 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 19:24:32 +00:00
Bob Wilson
14b2141497
When expanding a vector_shuffle, the element type may not be legal and may
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need to be promoted. The BUILD_VECTOR and EXTRACT_VECTOR_ELT nodes generated
here already allow the promoted type to be used without further changes, so
just do the promotion. This fixes part of pr7167.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104141 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 18:48:32 +00:00
Daniel Dunbar
d94406a940
MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 17:20:58 +00:00
Daniel Dunbar
52322e7b8b
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
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prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 15:26:43 +00:00
Daniel Dunbar
7d4bd203be
MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and
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CALL64pcrel32, for the same reason.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 08:07:12 +00:00
Evan Cheng
9085f98b32
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 07:28:01 +00:00
Evan Cheng
27fa722311
Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 07:26:50 +00:00
Daniel Dunbar
597f17d5f1
MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 06:20:44 +00:00
Evan Cheng
5fd1c9be2d
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 06:07:03 +00:00
Evan Cheng
3c3195cbf1
Target instruction selection should copy memoperands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 06:06:09 +00:00
Daniel Dunbar
9248b3208a
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
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avoid same prefix byte problem as in r104062.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 04:31:36 +00:00
Evan Cheng
ea420b20d4
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:52:25 +00:00
Dan Gohman
86026cd24e
Add a comment explaining why this code uses Append mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:21:34 +00:00
Evan Cheng
0a942dbb1e
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
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The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:08:17 +00:00
Dan Gohman
7c2e03916c
Factor out the code for picking integer arithmetic with immediate
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opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 00:53:19 +00:00
Dan Gohman
57aaa0b264
Add a comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104089 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 23:55:57 +00:00
Dan Gohman
360026f07f
Fix the predicate which checks for non-sensical formulae which have
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constants in registers which partially cancel out their immediate fields.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104088 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 23:48:08 +00:00
Dan Gohman
b2df433f71
Factor out the code for recomputing an LSRUse's Regs set after some
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of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104087 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 23:42:37 +00:00
Bob Wilson
417d1705bb
Fix a crash when debugging the coalescer. DebugValue instructions are not
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in the coalescer's instruction map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104086 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 23:19:42 +00:00
Dan Gohman
d079c300ed
Factor out code for estimating search space complexity into a helper
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function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:51:59 +00:00
Dan Gohman
0da751baf7
Add some more debug output.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:41:32 +00:00
Dan Gohman
d69d62833a
Factor out the code for deleting a formula from an LSRUse into
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a helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104079 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:39:15 +00:00
Dan Gohman
6458ff9230
Make some debug output more informative.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:37:37 +00:00
Dan Gohman
c4cfbaf217
Print an error message in Formula::print if the HasBaseReg flag
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is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104077 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:35:55 +00:00
Dan Gohman
90bb355b16
Rename RegUseTracker's RegUses member to RegUsesMap to avoid
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confusion with LSRInstance's RegUses member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:33:00 +00:00
Jakob Stoklund Olesen
dcf7708ad9
Remember to update VirtRegLastUse when spilling without killing before a call.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:20:09 +00:00
Dan Gohman
f8c1ef0510
Teach mode load folding and unfolding code about CMP32ri8 and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:54:15 +00:00
Bill Wendling
2abc93d0fb
Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is
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specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:47:08 +00:00
Dan Gohman
e5efbafdac
When converting a test to a cmp to fold a load, use the cmp that has an
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8-bit immediate field rather than one with a wider immediate field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:42:03 +00:00
Chris Lattner
6db0363bdc
make mcinstlower remove all but the first operand to CALL64pcrel32.
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The register use operands (e.g. the first argument is passed in a
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use. This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.
This fixes rdar://7998435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104062 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:40:18 +00:00
Evan Cheng
28dad2a5ca
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:31:17 +00:00
Eric Christopher
011c3f110b
Implement EmitTBSSSymbol for MachOStreamer.
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Fixes build failure as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:26:41 +00:00
Eric Christopher
4d01cbe93b
Make EmitTBSSSymbol take a section argument so that we can find it later.
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Fix up callers and users.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:16:04 +00:00
Jakob Stoklund Olesen
0eeb05c969
Properly handle multiple definitions of a virtual register in the same
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instruction.
This can happen on ARM:
>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:10:50 +00:00
Evan Cheng
5012f9b825
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 20:07:47 +00:00
Evan Cheng
27e4840e03
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 20:03:28 +00:00
Kevin Enderby
9f2ad11624
Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and not
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CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 18:09:20 +00:00
Kevin Enderby
d8ba292c9b
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
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correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104038 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:51:35 +00:00
Jakob Stoklund Olesen
6a8d2c6119
Teach the machine code verifier to use getSubRegisterRegClass().
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The old approach was wrong. It had an off-by-one error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104034 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:31:12 +00:00
Daniel Dunbar
2ae4bfd769
MC/Mach-O: Implement support for setting indirect symbol table offset in section header.
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Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:28:24 +00:00
Daniel Dunbar
56279f42b6
MC/Mach-O: Remove some FIXMEs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104032 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:28:20 +00:00
Daniel Dunbar
ca1212de59
MC/Mach-O: Fail faster/harder when we see .file, which isn't yet supported.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:28:17 +00:00
Daniel Dunbar
3f40b31256
MC/X86: Implement custom lowering to make sure we match things like
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X86::ADC32ri $0, %eax
to
X86::ADC32i32 $0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:22:24 +00:00