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2 Commits

Author SHA1 Message Date
Zoran Jovanovic
2365c029a9 [mips] Addition of a third operand to the instructions [d]div, [d]divu 
Author: obucina
Reviewers: dsanders
Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register
Differential Revision: http://reviews.llvm.org/D16888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269636 91177308-0d34-0410-b5e6-96231b3b80d8
 2016-05-16 08:57:59 +00:00
Daniel Sanders
4cf069b48d [mips] Added support for the div, divu, ddiv and ddivu macros which use traps and breaks in the integrated assembler. 
Summary:

Patch by Scott Egerton

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11675


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246763 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-03 12:31:22 +00:00