Commit Graph

33708 Commits

Author SHA1 Message Date
MinSeong Kim
eaca36fc81 [AArch64] Add support for Samsung Exynos-M1
Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A).

Differential Revision: http://reviews.llvm.org/D15663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256828 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-05 12:51:59 +00:00
David Majnemer
a3d4e67e43 [SimplifyCFG] Further improve our ability to remove redundant catchpads
In r256814, we managed to remove catchpads which were trivially redudant
because they were the same SSA value.  We can do better using the same
algorithm but with a smarter datastructure by hashing the SSA values
within the catchpad and comparing them structurally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256815 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-05 07:42:17 +00:00
David Majnemer
a4824774dc [SimplifyCFG] Remove redundant catchpads
Remove duplicate catchpad handlers from a catchswitch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256814 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-05 06:27:50 +00:00
Tom Stellard
b5659367ca AMDGPU/SI: Select non-uniform constant addrspace loads to flat instructions for HSA
Summary: This fixes a regression caused by r256282.

Reviewers: arsenm, cfang

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15736

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256810 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-05 03:40:16 +00:00
Joseph Tremoulet
d28c1bc303 [WinEH] Simplify unreachable catchpads
Summary:
At least for CoreCLR, a catchpad which immediately executes an
`unreachable` instruction indicates that the exception can never have a
matching type, and so such catchpads can be removed, and so can their
catchswitches if the catchswitch becomes empty.

Reviewers: rnk, andrew.w.kaylor, majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D15846

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256809 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-05 02:37:41 +00:00
David Majnemer
7f4aa70ca5 Revert "[X86] Use push-pop for materializing small constants under 'minsize'"
The red zone consists of 128 bytes beyond the stack pointer so that the
allocation of objects in leaf functions doesn't require decrementing
rsp.  In r255656, we introduced an optimization that would cheaply
materialize certain constants via push/pop.  Push decrements the stack
pointer and stores it's result at what is now the top of the stack.
However, this means that using push/pop would encroach on the red zone.
PR26023 gives an example where this corrupts an object in the red zone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256808 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-05 02:32:06 +00:00
Matthias Braun
8eb12ac26e X86: Add a testcase for PR25951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256801 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-05 00:48:16 +00:00
Matthias Braun
96b46d19c0 MachineInstrBundle: Fix reversed isSuperRegisterEq() call
Unfortunately this fix had the effect of exposing the
-verify-machineinstrs FIXME of X86InstrInfo.cpp in two testcases for
which I disabled it for now.
Two testcases also have additional pushq/popq where the corrected code
cannot prove that %rax is dead any longer. Looking at the examples, this
could potentially be fixed by improving computeRegisterLiveness() to check
the live-in lists of the successors blocks when reaching the end of a
block.

This fixes http://llvm.org/PR25951.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256799 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-05 00:45:35 +00:00
Nicolai Haehnle
fac1bfe37d AMDGPU: add +xnack feature
Summary:
Enabling this feature will account for the two SGPRs used by the hardware
to store the XNACK_MASK physically.

The hardware only requires this reservation when the XNACK feature is
explicitly enabled. At some point, HSA will probably want to do that, but
it does increase SGPR register pressure, so leave it disabled by default
for now (but do add a small test).

Reviewers: arsenm, tstellarAMD

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15869

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256794 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 23:35:53 +00:00
Chen Li
bee229d85d [InstructionCombining] prepareICWorklistFromFunction halts in infinite loop with instructions of token type
Summary: This patch fixes a bug in prepareICWorklistFromFunction, where the loop becomes infinite with instructions of token type. The patch checks if the instruction is token type, and if so it updates EndInst with the current instruction.

Reviewers: reames, majnemer

Subscribers: llvm-commits, sanjoy

Differential Revision: http://reviews.llvm.org/D15859

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256792 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 23:28:57 +00:00
David Majnemer
5216ace86d [LICM] Fix a small oversight introduced in r256763
r256763 had promoteLoopAccessesToScalars check for the existence of a
catchswitch when the exit blocks were populated but
promoteLoopAccessesToScalars may be called with a prepopulated set of
exit blocks which would also need to be checked.

This fixes PR26019.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256788 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 23:16:22 +00:00
Philip Reames
e14c161b0e [MemoryBuiltins] Remove isOperatorNewLike by consolidating non-null inference handling
This patch removes the isOperatorNewLike predicate since it was only being used to establish a non-null return value and we have attributes specifically for that purpose with generic handling. To keep approximate the same behaviour for existing frontends, I added the various operator new like (i.e. instances of operator new) to InferFunctionAttrs. It's not really clear to me why this isn't handled in Clang, but I didn't want to break existing code and any subtle assumptions it might have.

Once this patch is in, I'm going to start separating the isAllocLike family of predicates. These appear to be being used for a mixture of things which should be more clearly separated and documented. Today, they're being used to indicate (at least) aliasing facts, CSE-ability, and default values from an allocation site.

Differential Revision: http://reviews.llvm.org/D15820



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256787 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 22:49:23 +00:00
Simon Pilgrim
472704020c [X86][SSE] Ensure BLENDPD/BLENDPS/PBLEND inputs are both of the correct input type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256782 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 21:41:11 +00:00
Aditya Nandakumar
3c91dc3b09 Remove dead instructions before Redoing
Before reevaluating instructions, iterate over all instructions
to be reevaluated and remove trivially dead instructions and if
any of it's operands become trivially dead, mark it for deletion
until all trivially dead instructions have been removed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256773 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 19:48:14 +00:00
Geoff Berry
a1c12525dc [AArch64] Optimize some simple TBZ/TBNZ cases.
Summary:
Add some AArch64 dag combines to optimize some simple TBZ/TBNZ cases:

 (tbz (and x, m), b) -> (tbz x, b)
 (tbz (shl x, c), b) -> (tbz x, b-c)
 (tbz (shr x, c), b) -> (tbz x, b+c)
 (tbz (xor x, -1), b) -> (tbnz x, b)

Reviewers: jmolloy, mcrosier, t.p.northover

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D15702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256765 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 18:55:47 +00:00
David Majnemer
f34e40f4b4 [LICM] Don't insert instructions after a catchswitch when performing loop promotion
Inserting after a catchswitch results in verifier errors, bail out on
promotion if a catchswitch is a loop exit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256763 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 17:42:19 +00:00
Joseph Tremoulet
7f410b17a7 [WinEH] Update CoreCLR EH state numbering
Summary:
Fix the CLR state numbering to generate correct tables, and update the lit
test to verify them.

The CLR numbering assigns one state number to each catchpad and
cleanuppad.

It also computes two tree-like relations over states:
 1) Each state has a "HandlerParentState", which is the state of the next
    outer handler enclosing this state's handler (same as nearest ancestor
    per the ParentPad linkage on EH pads, but skipping over catchswitches).
 2) Each state has a "TryParentState", which:
    a) for a catchpad that's not the last handler on its catchswitch, is
       the state of the next catchpad on that catchswitch.
    b) for all other pads, is the state of the pad whose try region is the
       next outer try region enclosing this state's try region.  The "try
       regions are not present as such in the IR, but will be inferred
       based on the placement of invokes and pads which reach each other
       by exceptional exits.

Catchswitches do not get their own states, but each gets mapped to the
state of its first catchpad.

Table generation requires each state's "unwind dest" state to have a lower
state number than the given state.

Since HandlerParentState can be computed as a function of a pad's
ParentPad, and TryParentState can be computed as a function of its unwind
dest and the TryParentStates of its children, the CLR state numbering
algorithm first computes HandlerParentState in a top-down pass, then
computes TryParentState in a bottom-up pass.

Also reword some comments/names in the CLR EH table generation to make the
distinction between the different kinds of "parent" clear.


Reviewers: rnk, andrew.w.kaylor, majnemer

Subscribers: AndyAyers, llvm-commits

Differential Revision: http://reviews.llvm.org/D15325

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256760 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 16:16:01 +00:00
Michael Zuckerman
09816bb549 [AVX512] add PSRAD and PSRAQ Intrinsic
Differential Revision: http://reviews.llvm.org/D15851



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256754 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 13:45:45 +00:00
Michael Zuckerman
ab0aa0e9d9 [AVX512] add PSRAW Intrinsic
Differential Revision: http://reviews.llvm.org/D15850



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256751 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 12:50:36 +00:00
Michael Zuckerman
5b63de585b [AVX512] add PSRLV Intrinsic
Differential Revision: http://reviews.llvm.org/D15838



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256747 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 11:39:06 +00:00
David Majnemer
82e76d50b1 [LICM] Make instruction sinking funclet-aware
We had two bugs here:
- We might try to sink into a catchswitch, causing verifier failures.
- We will succeed in sinking into a cleanuppad but we didn't update the
  funclet operand bundle.

This fixes PR26000.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256728 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-04 03:37:39 +00:00
Dimitry Andric
e135ddf4bb Fix one file that I didn't convert properly in r256707.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256720 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-03 22:33:32 +00:00
Simon Pilgrim
5da99c7bd4 [X86][MMX] Regenerated vector insertion test.
Shows the true horror of what is going on....

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256713 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-03 19:17:37 +00:00
Simon Pilgrim
0dd2ca765d [X86][SSE] Added tests for insertion of zero elements into vectors
Many of these could be much better if we just lowered them all as shuffles - especially for the 256-bit vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256708 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-03 17:33:32 +00:00
Dimitry Andric
ac6a87b06e Fix several accidental DOS line endings in source files
Summary:
There are a number of files in the tree which have been accidentally checked in with DOS line endings.  Convert these to native line endings.

There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those.

Reviewers: joerg, aaron.ballman

Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15848

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256707 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-03 17:22:03 +00:00
Simon Pilgrim
c88a575ea5 [X86][SSE41] Added test cases for improving insertps shuffles
As mentioned on D14261, an upcoming patch will improve combines of insertps instructions. 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256706 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-03 17:14:15 +00:00
Simon Pilgrim
85b6d5e1dd [X86][SSE] Added v4f32 shuffle with zero tests
This is mainly test cases for improvements to insertps matching, but pre-SSE41 shuffles could be improved as well

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256705 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-03 17:02:56 +00:00
Joseph Tremoulet
4505d54875 [WinEH] Verify catchswitch handlers
Summary:
The handler list must be nonempty and consist solely of CatchPads.


Reviewers: rnk, andrew.w.kaylor, majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D15842

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256691 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-02 15:25:25 +00:00
Joseph Tremoulet
3c6a15b1cc [WinEH] Tighten parentPad verifier checks
Summary: A catchswitch cannot be a parent of a cleanuppad or another catchswitch.

Reviewers: rnk, andrew.w.kaylor, majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D15841

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256690 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-02 15:24:24 +00:00
Joseph Tremoulet
d5ab13d966 [WinEH] Update catchrets with cloned successors
Summary:
Add a pass to update catchrets when their successors get cloned; the
existing pass doesn't catch these because it walks the funclet whose
blocks are being cloned but the catchret is in a child funclet.

Also update the test for removing incoming PHI values; when the
predecessor is a catchret, the relevant color is the catchret's parentPad,
not its block's color.


Reviewers: andrew.w.kaylor, rnk, majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D15840

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256689 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-02 15:22:36 +00:00
David Majnemer
19d1ebc725 [X86] Add intrinsics for reading and writing to the flags register
LLVM's targets need to know if stack pointer adjustments occur after the
prologue.  This is needed to correctly determine if the red-zone is
appropriate to use or if a frame pointer is required.

Normally, LLVM can figure this out very precisely by reasoning about the
contents of the MachineFunction.  There is an interesting corner case:
inline assembly.

The vast majority of inline assembly which will perform a push or pop is
done so to pair up with pushf or popf as appropriate.  Unfortunately,
this inline assembly doesn't mark the stack pointer as clobbered
because, well, it isn't.  The stack pointer is decremented and then
immediately incremented.  Because of this, LLVM was changed in r256456
to conservatively assume that inline assembly contain a sequence of
stack operations.  This is unfortunate because the vast majority of
inline assembly will not end up manipulating the stack pointer in any
way at all.

Instead, let's provide a more principled solution: an intrinsic.
FWIW, other compilers (MSVC and GCC among them) also provide this
functionality as an intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256685 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-01 06:50:01 +00:00
Sanjay Patel
e193ff319c [LibCallSimplifier] propagate FMF when shrinking binary calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256682 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-31 23:40:59 +00:00
Sanjay Patel
2e3f468f86 [LibCallSimplifier] propagate FMF when shrinking unary calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256679 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-31 21:52:31 +00:00
Sanjay Patel
36bfd300cd change function names to avoid accidentally matching the substring
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256678 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-31 21:25:25 +00:00
Sanjay Patel
f6e2baf532 add 'fast' attribute to calls to show that the flag isn't being propagated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256677 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-31 21:12:19 +00:00
Michael Zuckerman
6edca6938a [AVX512] add PSRLQ and PSRLD Intrinsic
Differential Revision: http://reviews.llvm.org/D15770


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256673 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-31 15:22:04 +00:00
Michael Kuperstein
4f73c42797 [X86] Avoid folding scalar loads into unary sse intrinsics
Not folding these cases tends to avoid partial register updates:
sqrtss (%eax), %xmm0
Has a partial update of %xmm0, while
movss (%eax), %xmm0
sqrtss %xmm0, %xmm0
Has a clobber of the high lanes immediately before the partial update,
avoiding a potential stall.

Given this, we only want to fold when optimizing for size.
This is consistent with the patterns we already have for some of
the fp/int converts, and in X86InstrInfo::foldMemoryOperandImpl()

Differential Revision: http://reviews.llvm.org/D15741

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256671 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-31 09:45:16 +00:00
Asaf Badouh
7b8bd88d45 [X86][PKU] Add {RD,WR}PKRU intrinsics
Differential Revision: http://reviews.llvm.org/D15808

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256670 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-31 08:31:13 +00:00
Sanjay Patel
08e3bf995e [ValueTracking] fix bug computing isKnownToBeAPowerOfTwo() with arithmetic shift right (PR25900)
This is a fix for:
https://llvm.org/bugs/show_bug.cgi?id=25900

If we think that an arithmetic right shift of a power of two is always a power of two, 
an sdiv gets wrongly converted to udiv.

Differential Revision: http://reviews.llvm.org/D15827



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256655 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-30 22:40:52 +00:00
Geoff Berry
7a39479674 [JumpThreading] Fix opcode bonus in getJumpThreadDuplicationCost()
The code that was meant to adjust the duplication cost based on the
terminator opcode was not being executed in cases where the initial
threshold was hit inside the loop.

Subscribers: mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D15536

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256568 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-29 18:10:16 +00:00
Michael Zuckerman
48d1be172b [AVX512] add PSRLW Intrinsic
Differential Revision: http://reviews.llvm.org/D15751


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256558 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-29 13:04:35 +00:00
James Y Knight
c1b271062b Fix gold test after r256465.
That commit added a new pass, and this test is sensitive to what the
first pass after verify is called.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256532 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-29 03:48:37 +00:00
Eric Christopher
8d5b76e5d4 Accept dwarf version 5 for CIE versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256527 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-28 23:02:42 +00:00
Artyom Skrobov
1714cbd44c [Thumb] Fix assembler error 'cannot honor width suffix pop {lr}'
Summary:
* avoid generating POP {LR} in Thumb1 epilogues
* combine MOV LR, Rx + BX LR -> BX Rx in a peephole optimization pass
* combine POP {LR} + B + BX LR -> POP {PC} on v5T+

Test cases by Ana Pazos

Differential Revision: http://reviews.llvm.org/D15707

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256523 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-28 21:40:45 +00:00
Sanjay Patel
a5063429b2 [x86] lower calls to fmin and llvm.minnum.* using minss/minsd/minps/minpd (PR24475)
This is a follow-on to:
http://reviews.llvm.org/rL255700
http://reviews.llvm.org/rL256454
http://reviews.llvm.org/rL256510



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256522 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-28 21:16:55 +00:00
Manuel Jacob
912373de69 [RS4GC] Fix rematerialization of bitcast of bitcast.
Summary:
Previously, only the outer (last) bitcast was rematerialized, resulting in a
use of the unrelocated inner (first) bitcast after the statepoint.  See the
test case for an example.

Reviewers: igor-laevsky, reames

Subscribers: reames, alex, llvm-commits, sanjoy

Differential Revision: http://reviews.llvm.org/D15789

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-28 20:14:05 +00:00
Elena Demikhovsky
84f6badccc Implemented cost model for masked gather and scatter operations
The cost is calculated for all X86 targets. When gather/scatter instruction
is not supported we calculate the cost of scalar sequence.

Differential revision: http://reviews.llvm.org/D15677



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256519 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-28 20:10:59 +00:00
Sanjay Patel
5fb72b3250 [x86] lower calls to fmax and llvm.maxnum.* using maxps/maxpd (PR24475)
This is a follow-on to:
http://reviews.llvm.org/rL255700
http://reviews.llvm.org/rL256454



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256510 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-28 19:20:19 +00:00
Sanjay Patel
3e50893e8e Specify triple so 'make check' passes on darwin x86-64
The check lines were added with:
http://reviews.llvm.org/rL256458
http://reviews.llvm.org/rL256460

but on a darwin target, the output looks like:
  ## InlineAsm Start
  rorq  %rdi
  ## InlineAsm End
  ## InlineAsm Start
  rorq  %rsi
  ## InlineAsm End
  leaq  (%rsi,%rdi), %rax
  retq




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256507 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-28 18:28:44 +00:00
Roman Divacky
d1070bbc62 Support clrex instruction on ARMv6k. Patch by Andrew Turner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256505 91177308-0d34-0410-b5e6-96231b3b80d8
2015-12-28 17:47:23 +00:00