Commit Graph

2727 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
ec572539dd Add TableGen support for callee saved registers.
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 22:46:58 +00:00
Devang Patel
40bced0306 Intel syntax: Ignore mnemonic aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 18:30:45 +00:00
David Blaikie
58bd1510a4 Provide better messages in llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 07:00:13 +00:00
David Blaikie
fdebc38523 Remove unreachable code. (replace with llvm_unreachable to help GCC where necessary)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 04:43:56 +00:00
David Blaikie
2dd674fdce Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148262 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-16 23:24:27 +00:00
Jakob Stoklund Olesen
794481d5ca Skip the NAME field when forming tuples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148147 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 22:23:50 +00:00
Jakob Stoklund Olesen
8dd6f0c835 Delete CodeInit and CodeRecTy from TableGen.
The code type was always identical to a string anyway. Now it is simply
a synonym. The code literal syntax [{...}] is still valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 03:38:34 +00:00
Pete Cooper
ddfda5cd16 Added MVT::v2f16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-12 23:14:13 +00:00
Devang Patel
56315d319c Record asm variant id in MatchEntry and check it while matching instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147858 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10 17:50:43 +00:00
David Blaikie
2bd335470f Remove unnecessary default cases in switches that cover all enum values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10 16:47:17 +00:00
Devang Patel
d06b01c038 Use descriptive variable name and remove incorrect operand number check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09 21:30:46 +00:00
Devang Patel
0dbcadaa2f Split AsmParser into two components - AsmParser and AsmParserVariant
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09 19:13:28 +00:00
Benjamin Kramer
f321e1075e Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 19:42:13 +00:00
Cameron Zwarich
82f000266a Fix TableGen so that it will emit the correct signature for FastEmit_f:
/// FastEmit_f - This method is called by target-independent code
  /// to request that an instruction with the given type, opcode, and
  /// floating-point immediate operand be emitted.
  virtual unsigned FastEmit_f(MVT VT,
                              MVT RetVT,
                              unsigned Opcode,
                              const ConstantFP *FPImm);

Currently, it emits an accidentally overloaded version without the const on the
ConstantFP*. This doesn't affect anything in the tree, since nothing causes that
method to be autogenerated, but I have been playing with some ARM TableGen
refactorings that hit this problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 08:18:37 +00:00
Devang Patel
63faf82d03 Refactor.
Store AsmParser info locally. A small step towards emitting match entries for multiple asm variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147710 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 01:33:34 +00:00
Devang Patel
b78307fc58 Eliminate an error check that may not work with all asm syntax variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 01:22:23 +00:00
Devang Patel
59f7ee0400 Do not hard code asm variant number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147583 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05 00:51:28 +00:00
Jakob Stoklund Olesen
ac1ed44d95 Don't use enums larger than 1 << 31 for target features.
Patch by Andy Zhang!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147491 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 23:04:28 +00:00
Craig Topper
06f554d06a Add disassembler support for VPERMIL2PD and VPERMIL2PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 06:23:39 +00:00
Craig Topper
e6a3a2990e Add FMA4 instructions to disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-30 05:20:36 +00:00
Jim Grosbach
4050bc4cab ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:19:05 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:38:54 +00:00
Chandler Carruth
cfb75fba73 Fix up the CMake build for the new files added in r146960, they're
likely to stay either way that discussion ends up resolving itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 08:42:11 +00:00
David Blaikie
0c271bccf7 Revert pragma clang suppressions that confuse GCC. (I'll worry about how to suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 08:22:49 +00:00
David Blaikie
2d24e2a396 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 02:50:00 +00:00
Dan Gohman
e3376ecd50 Add basic generic CodeGen support for half.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 00:02:33 +00:00
Jakob Stoklund Olesen
570f9a972e Emit a getMatchingSuperRegClass() implementation for every target.
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 16:53:34 +00:00
Jakob Stoklund Olesen
a9f65b9a1f Synthesize register classes for TRI::getMatchingSuperRegClass().
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results.  The function is
still not auto-generated, so it still returns inexact results.

This produces these new register classes:

ARM:
    QQPR_with_dsub_0_in_DPR_8
    QQQQPR_with_dsub_0_in_DPR_8
X86:
    GR64_with_sub_32bit_in_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
    GR64_with_sub_16bit_in_GR16_NOREX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
    GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
    GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
    GR64_with_sub_32bit_in_GR32_TC
    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
    GR64_with_sub_32bit_in_GR32_AD
    GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX

The other targets in the tree are not weird enough to be affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 16:53:28 +00:00
Jakob Stoklund Olesen
fec33444c5 Extract a method. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-16 00:12:05 +00:00
Jakob Stoklund Olesen
d4c826f648 Use the proper comparator for set_intersection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 19:26:23 +00:00
Jakob Stoklund Olesen
7e56831a68 Synthesize missing register class intersections.
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B.  This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.

In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).

This introduces these synthetic register classes:

ARM:
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    tGPR_and_tcGPR
    hGPR_and_tcGPR

X86:
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR64_NOSP_and_GR64_TC
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_TC
    GR32_NOAX_and_GR32_NOSP
    GR64_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_ABCD_and_GR32_NOAX
    GR64_ABCD_and_GR64_TC
    GR32_NOAX_and_GR32_TC
    GR32_AD_and_GR32_NOAX

Other targets are unaffected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 16:48:55 +00:00
Daniel Dunbar
4ab406d7fc LLVMBuild: Remove trailing newline, which irked me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 19:48:00 +00:00
Jakob Stoklund Olesen
1b3d218880 Extract a method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146374 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-12 16:16:24 +00:00
Jim Grosbach
3b8991cc98 ARM: NEON SHLL instruction immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 01:07:24 +00:00
Jim Grosbach
a66512e591 Extend AsmMatcher token literal matching to allow aliasing.
For example, ARM allows:
    vmov.u32 s4, #0  -> vmov.i32, #0
'u32' is a more specific designator for the 32-bit integer type specifier
and is legal for any instruction which accepts 'i32' as a datatype suffix.

We want to say,
    def : TokenAlias<".u32", ".i32">;

This works by marking the match class of 'From' as a subclass of the
match class of 'To'.

rdar://10435076



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 23:43:54 +00:00
Evan Cheng
7c2a4a30e0 First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:12:01 +00:00
Jim Grosbach
3d5d8f6b76 Tidy up. Fix naming convention stuff for some internal functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145974 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 22:07:02 +00:00
Sebastian Pop
464f3a332f use space star instead of star space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145944 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 17:34:16 +00:00
Sebastian Pop
f6f77e90a1 add missing point at the end of sentences
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 17:34:11 +00:00
Jim Grosbach
587f5062b9 ARM NEON VEXT aliases for data type suffices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 23:34:39 +00:00
Dylan Noblesmith
85bef06a2e TableGen: fix CMake build s'more
Oops, missed another missing file from r145629.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 21:53:39 +00:00
Anshuman Dasgupta
dc81e5da27 Add a deterministic finite automaton based packetizer for VLIW architectures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145629 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 21:10:21 +00:00
Jim Grosbach
4a2242cea0 Replace an assert() with an actual diagnostic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 23:16:25 +00:00
Jim Grosbach
13af222bab ARM parsing for VLD1 two register all lanes, no writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 18:21:25 +00:00
Jim Grosbach
d4578a4f8d llvm_unreachable() is not for user diagnostics....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145465 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 01:15:55 +00:00
Jim Grosbach
98b05a57b6 ARM parsing aliases for VLD1 single register all lanes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 01:09:44 +00:00
Craig Topper
787a88ff18 Remove some unnecessary filtering checks from X86 disassembler table build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-19 05:48:20 +00:00
Owen Anderson
99aa14ff64 Rename MVT::untyped to MVT::Untyped to match similar nomenclature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 01:02:57 +00:00
Evan Cheng
eaa192af18 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
integer variants. rdar://10437054


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 02:12:34 +00:00
Jim Grosbach
bfc9429c2b ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
rdar://10435076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 01:46:57 +00:00