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1777 Commits

Author SHA1 Message Date
Chris Lattner
47b4a9b2e0 Minor code cleanups 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4814 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 21:04:50 +00:00
Chris Lattner
1804233ca5 Implement printing of store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4813 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 21:03:39 +00:00
Chris Lattner
3d3067bf6b The big change here is to handle printing/emission of X86II::MRMSrcMem 
instructions.  Right now the only users are load instructions, and Misha's
spill code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4812 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 20:44:15 +00:00
Chris Lattner
92845e37f5 Remove implicit information from instruction selector 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4811 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 18:54:29 +00:00
Chris Lattner
457adb55f9 Add printing information for MUL and DIV 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4810 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 18:54:14 +00:00
Chris Lattner
94e8ee2282 Fix a bug that prevented compilation of multiple functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4809 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:26:58 +00:00
Chris Lattner
d3e0faca06 Remove opcode information for instructions that are completely defined now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4805 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:12:55 +00:00
Chris Lattner
644e3261d1 Add printing support for sahf & setcc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4804 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:10:57 +00:00
Chris Lattner
675dd2cc47 Add printing support for /0 /1 type instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4803 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:09:01 +00:00
Chris Lattner
85b39f229f Add support for /0 /1, etc type instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4802 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 17:08:49 +00:00
Chris Lattner
4b4e9dd937 Rename the SetCC X86 instructions to reflect the fact that they are the 
register versions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4800 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 16:19:42 +00:00
Chris Lattner
05093a51b4 Simplify setcc code a bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4799 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 15:52:38 +00:00
Chris Lattner
77875d88d0 Support Registers of the form (B8+ rd) for example 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4798 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 02:00:20 +00:00
Chris Lattner
97ad9e1fea Dont' set flags 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4797 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 01:59:50 +00:00
Chris Lattner
233ad71051 Implement printing more, implement opcode output more 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4796 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 01:33:44 +00:00
Chris Lattner
0dc20dda5b Huge diff do to reindeinting comments. 
Basically just adds OpSize flags for instructions that need them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4795 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 01:33:28 +00:00
Chris Lattner
11e53e3c38 Add new prefix flag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4794 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 01:32:55 +00:00
Chris Lattner
644e1abae4 Print another class of instructions correctly, giving us: xorl EDX, EDX 
for example.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4793 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 00:30:01 +00:00
Misha Brukman
7c58925050 Booleans are types too. And they get stored in bytes. And InstructionSelection 
doesn't assert fail. And everyone's happy. Yay!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4792 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-21 00:25:56 +00:00
Misha Brukman
b83b28697c Add definitions for function headers from MRegisterInfo.h: 
Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4784 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:59:43 +00:00
Misha Brukman
e1f0d8113a Check not only for MO_VirtualRegister, but MO_MachineRegister as well when 
printing out assembly. After all, we want the real thing too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4783 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 18:56:41 +00:00
Misha Brukman
d2cc017f46 Add mapping in MachineFunction from SSA regs to Register Classes. Also, 
uncovered a bug where registers were not being put in a map if they were not
found...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4776 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 00:58:23 +00:00
Misha Brukman
90ed18c201 Sigh. Fixed some speling. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4775 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 00:56:42 +00:00
Misha Brukman
602b9ff595 Thanks to the R8, R16, and R32 macros, I can now deal with registers that 
belong to different register classes easier.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4773 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-20 00:47:40 +00:00
Brian Gaeke
c03a0cb01b Brian Gaeke says: 
lib/Target/X86/InstSelectSimple.cpp: Add a little something to
 visitBranchInst which supports conditional branches.
lib/Target/X86/X86InstrInfo.def: Add defs of JNE, JE, CMPri8


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4755 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-19 09:08:47 +00:00
Chris Lattner
f9f6088e17 Start trying to print instructions more correctly. For now we also print out the opcode for each instruction as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4743 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-18 06:56:51 +00:00
Chris Lattner
f21dfcddcf Expose base opcode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4742 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-18 06:56:24 +00:00
Chris Lattner
6aab9cf65c Start to add more information to instr.def 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4741 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-18 05:37:11 +00:00
Chris Lattner
239dcfd215 Add instruction annotation about whether it has a 0x0F opcode prefix 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4740 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-18 01:59:28 +00:00
Chris Lattner
9213b73c19 Add more void flags 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4739 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-18 01:37:48 +00:00
Chris Lattner
92bd0f9c4d Set the void flag on instructions that should get it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4738 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-18 01:34:36 +00:00
Chris Lattner
927dd095c4 Arrange to have a TargetMachine available in X86InstrInfo::print 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4734 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 23:20:37 +00:00
Chris Lattner
e9b309ad13 Wow, I'm incapable of the simplest things today... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4732 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 23:05:21 +00:00
Chris Lattner
fb02a8b11f Rename registers to follow the intel style of all caps 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4731 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 23:03:46 +00:00
Chris Lattner
dbb61c6445 Reorganize printing interface a bit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4728 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 22:53:13 +00:00
Chris Lattner
71e83caecd Fix minor detail 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4725 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 22:33:26 +00:00
Chris Lattner
0692536b71 Fix Mul/Div clobbers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4718 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 21:56:38 +00:00
Chris Lattner
6fc3c52359 Fix a few typos, implement load/store 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4716 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 21:11:55 +00:00
Chris Lattner
9562add237 Add functions to buld X86 specific constructs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4714 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 21:03:35 +00:00
Chris Lattner
1411ba31ba Add information about memory index representation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4712 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 20:33:26 +00:00
Chris Lattner
e7236ffa94 Add load/store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4711 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 20:33:12 +00:00
Chris Lattner
43189d17c3 Switch visitRet to use getClass() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4710 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-17 20:07:45 +00:00
Brian Gaeke
6559bb96a9 include/llvm/CodeGen/MachineInstrBuilder.h: Add addClobber() inline 
convenience method.  Fix typo in comment.
lib/Target/X86/InstSelectSimple.cpp: Explicitly specify some implicit uses.
 Use MOVZX/MOVSX instead of MOV instructions with sign extend instructions.
 Take out LEAVE instructions.
 32-bit IDIV and DIV use CDQ, not CWQ (CWQ is a typo).
 Fix typo in comment and remove some FIXME comments.
lib/Target/X86/Printer.cpp: Include X86InstrInfo.h and llvm/Function.h.
 Add some simple code to Printer::runOnFunction to iterate over
  MachineBasicBlocks and call X86InstrInfo::print().
lib/Target/X86/X86InstrInfo.def: Make some more instructions with
 implicit defs "Void".  Add more sign/zero extending "move" insns
 (movsx, movzx).
lib/Target/X86/X86RegisterInfo.def: Add EFLAGS as a register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4707 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-14 22:32:30 +00:00
Brian Gaeke
20abb6bf45 InstSelectSimple.cpp: (visitReturnInst) Add return instructions with return 
values.
X86InstrInfo.def: add LEAVE instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4691 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-11 19:37:09 +00:00
Brian Gaeke
1749d6359b Add instruction selection code and tests for setcc instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4603 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-07 17:59:21 +00:00
Chris Lattner
f01729ea56 Implement signed and unsigned division and remainder 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4508 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 20:54:46 +00:00
Chris Lattner
ca9671d864 Implement multiply operator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4506 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 20:28:58 +00:00
Chris Lattner
68aad93291 * Implement subtract 
* Merge add code into logical code


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4503 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 20:13:22 +00:00
Chris Lattner
e2954c84e9 shuffle code around a bit, implement and, or, xor 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4502 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 20:04:26 +00:00
Chris Lattner
51b49a9633 Add PHI node support, add comment for branch function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4500 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 19:45:49 +00:00
Chris Lattner
2df035bb3c Implement unconditional branching support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4498 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 19:27:56 +00:00
Chris Lattner
e9913f2cff * Fix nonconstant shift case 
* Turn table into 2d table


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4496 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 01:41:55 +00:00
Chris Lattner
b1761fc4df Use a more table driven approach to handling types. Seems to simplify the 
code a bit


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4493 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 01:15:18 +00:00
Chris Lattner
d5a87f80b7 Make switch statements denser, but only because of the follow-on patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4492 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 00:49:56 +00:00
Chris Lattner
796df73e6e * Remove dead variable 
* Shift amount is always guaranteed to be 8 bits


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4491 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-11-02 00:44:25 +00:00
Brian Gaeke
a1719c9130 InstSelectSimple.cpp: Include llvm/iOther.h for ShiftInst. 
Add ISel::visitShiftInst() to instruction select shift instructions.
 Add a comment in visitAdd about how to do 64 bit adds.

X86InstrInfo.def: Add register-to-register move opcodes and shift opcodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4477 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-31 23:03:59 +00:00
Chris Lattner
cc0b0c59e8 Add lots more info 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4450 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-30 06:04:46 +00:00
Chris Lattner
8548ee75eb Make sure to set the destination register correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4444 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-30 01:49:01 +00:00
Chris Lattner
b752e9a2ae Set the destination register field based on the target specific flags 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4442 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-30 01:15:31 +00:00
Chris Lattner
9d17740295 Add flag to specify when no value is produced by an instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4441 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-30 01:09:34 +00:00
Chris Lattner
e5f5221b5e Implement the new optional getRegisterInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4437 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-30 00:56:18 +00:00
Chris Lattner
3dffa7953f Print machine code after instruction selection 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4434 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-30 00:47:49 +00:00
Chris Lattner
42c7786227 Make sure to pass the LLVM basic block in 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4433 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-30 00:47:40 +00:00
Chris Lattner
36b36037a3 Construct annotation, to make sure it's attached to function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4429 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-29 23:40:58 +00:00
Chris Lattner
b4f68ed32e Convert backend to use passes, implement X86TargetMachine 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4421 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-29 22:37:54 +00:00
Chris Lattner
055c965bff Rename X86InstructionInfo to X86InstrInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4413 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-29 21:05:24 +00:00
Chris Lattner
33f53b554a Minor renaming 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4410 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-29 20:48:56 +00:00
Chris Lattner
341a937169 Switch to generating machineinstr's instead of MInstructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4396 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-29 17:43:55 +00:00
Chris Lattner
a535fabe7d Be compatible with sparc backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4395 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-29 17:43:38 +00:00
Chris Lattner
9bbf439e38 Implement MachineInstrInfo interface 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4394 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-29 17:43:19 +00:00
Chris Lattner
79c033765c Switch to different flag set 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4393 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-29 17:42:40 +00:00
Chris Lattner
75276f150e Initial stab at MachineInstr'ication 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4367 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-28 23:55:19 +00:00
Misha Brukman
6ee9b5a57d Fixed spelling and grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4353 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-28 20:01:52 +00:00
Chris Lattner
6f8fd25697 Remove dead fixme 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4300 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-27 21:23:43 +00:00
Chris Lattner
c5291f5e0e Instruction select constant arguments correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4297 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-27 21:16:59 +00:00
Chris Lattner
65a78f28e3 Add instruction definitions for mov r, imm instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4296 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-27 21:16:44 +00:00
Chris Lattner
726140821f Initial checkin of X86 backend. 
We can instruction select exactly one instruction 'ret void'.  Wow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4284 91177308-0d34-0410-b5e6-96231b3b80d8
 2002-10-25 22:55:53 +00:00