43998 Commits

Author SHA1 Message Date
Diana Picus
f51d2756c0 [ARM] GlobalISel: Test hard float properly
It turns out -float-abi=hard doesn't set the hard float calling
convention for libcalls. We need to use a hard float triple instead
(e.g. gnueabihf).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299761 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 12:04:24 +00:00
Sam Kolton
218a5a7e27 [AMDGPU] Move SiShrinkInstruction and SDWAPeephole to SSAOptimization passes
Summary:
Difference beetween PreRegAlloc() and MachineSSAOptimization() are that the former is run despite of -O0 optimization level. In my undestanding SiShrinkInstructions and SDWAPeephole shouldn't run when optimizations are disabled.
With this change order of passes will not change.

Reviewers: arsenm, vpykhtin, rampitec

Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D31705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299757 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 10:53:12 +00:00
Diana Picus
aa39cd364d [ARM] GlobalISel: Support frem for 64-bit values
Legalize to a libcall.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299756 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 10:50:02 +00:00
Diana Picus
3afaea7b42 [ARM] GlobalISel: Support frem for 32-bit values
Legalize to a libcall.
On this occasion, also start allowing soft float subtargets. For the
moment G_FREM is the only legal floating point operation for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299753 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 09:41:39 +00:00
Craig Topper
826edb2ba1 [InstCombine] Handle more commuted cases of ((A & B) | ~A) -> (~A | B)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299747 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 07:32:00 +00:00
Craig Topper
ae892fe446 [InstCombine] Add additional tests with varied commuting to show missing combines. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299746 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 07:31:55 +00:00
Daniel Berlin
f634bfbb16 AliasAnalysis: Be less conservative about volatile than atomic.
Summary:
getModRefInfo is meant to answer the question "what impact does this
instruction have on a given memory location" (not even another
instruction).

Long debate on this on IRC comes to the conclusion the answer should be "nothing special".

That is, a noalias volatile store does not affect a memory location
just by being volatile.  Note: DSE and GVN and memdep currently
believe this, because memdep just goes behind AA's back after it says
"modref" right now.

see line 635 of memdep. Prior to this patch we would get modref there, then check aliasing,
and if it said noalias, we would continue.

getModRefInfo *already* has this same AA check, it just wasn't being used because volatile was
lumped in with ordering.

(I am separately testing whether this code in memdep is now dead except for the invariant load case)

Reviewers: jyknight, chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31726

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299741 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 01:28:36 +00:00
Craig Topper
1096080a5d [InstCombine] Add more commuted patterns to support folding ((~A & B) | A) -> (A | B).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299737 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 00:29:47 +00:00
Zachary Turner
b470610091 Allow specification of what kinds of class members to dump.
Previously when dumping class definitions, there were only
two modes - on or off.  But it's useful to sometimes get a
little more fine-grained.  For example, you might only want
to see the record layout (for example to look for extraneous
padding).  This patch adds a third mode, layout mode, which
does exactly that.  Only this-relative data members are
displayed in this mode.

Differential Revision: https://reviews.llvm.org/D31794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299733 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 23:43:39 +00:00
Konstantin Zhuravlyov
4d40c97796 AMDGPU/GFX9: Fix shared and private aperture queries
Differential Revision: https://reviews.llvm.org/D31786


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299727 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 23:02:33 +00:00
Craig Topper
42c1cc1993 [InstCombine] Add a few cases for OR we fail to optimize due to missing commuted patterns checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299725 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 23:00:22 +00:00
Eli Friedman
f25acacbe6 Turn on -addr-sink-using-gep by default.
The new codepath has been in the tree for years, and there isn't any
reason to use two codepaths here.

Differential Revision: https://reviews.llvm.org/D30596



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299723 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 22:42:18 +00:00
Michael Kuperstein
bf82f16ca4 [X86] Revert r299387 due to AVX legalization infinite loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299720 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 22:33:25 +00:00
Matt Arsenault
c82755f01b AMDGPU: Diagnose illegal SGPR to VGPR copies
This is possible in ways that are not compiler bugs,
so stop asserting on them.

This emits an extra error when emitting objects when it
can't encode the new pseudo, but I'm not sure that matters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299712 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 21:09:53 +00:00
Matt Arsenault
34d5677726 AMDGPU: Replace fp16SrcZerosHighBits with a whitelist
FCOPYSIGN is lowered to bit operations which don't clear the high
bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299708 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 20:58:30 +00:00
Keno Fischer
1f6fa0f45a [llvm-extract] Add option for recursive extraction
Summary:
Particularly, with --delete, this can be very useful for testing
new optimizations on some hotspots, without having to run it on the whole
application. E.g. as such:
```
llvm-extract app.bc --recursive --rfunc .*hotspot.* > hotspot.bc
llvm-extract app.bc --recursive --delete --rfunc .*hotspot.* > residual.bc
llc -filetype=obj residual.bc > residual.o
llc -filetype=obj hotspot.bc > hotspot.o
cc -o app residual.o hotspot.o
```

Reviewed By: davide
Differential Revision: https://reviews.llvm.org/D31722

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299706 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 20:51:40 +00:00
Huihui Zhang
e184e1f870 [SelectionDAG] [ARM CodeGen] Fix chain information of LowerMUL
In LowerMUL, the chain information is not preserved for the new
created Load SDNode.

For example, if a Store alias with one of the operand of Mul.
The Load for that operand need to be scheduled before the Store.
The dependence is recorded in the chain of Store, in TokenFactor.
However, when lowering MUL, the SDNodes for the new Loads for
VMULL are not updated in the TokenFactor for the Store. Thus the
chain is not preserved for the lowered VMULL.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299701 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 20:22:51 +00:00
Evgeniy Stepanov
7bfedca6fc [asan] Fix dead stripping of globals on Linux.
Use a combination of !associated, comdat, @llvm.compiler.used and
custom sections to allow dead stripping of globals and their asan
metadata. Sometimes.

Currently this works on LLD, which supports SHF_LINK_ORDER with
sh_link pointing to the associated section.

This also works on BFD, which seems to treat comdats as
all-or-nothing with respect to linker GC. There is a weird quirk
where the "first" global in each link is never GC-ed because of the
section symbols.

At this moment it does not work on Gold (as in the globals are never
stripped).

This is a re-land of r298158 rebased on D31358. This time,
asan.module_ctor is put in a comdat as well to avoid quadratic
behavior in Gold.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299697 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 19:55:17 +00:00
Evgeniy Stepanov
9d134816b4 [asan] Put ctor/dtor in comdat.
When possible, put ASan ctor/dtor in comdat.

The only reason not to is global registration, which can be
TU-specific. This is not the case when there are no instrumented
globals. This is also limited to ELF targets, because MachO does
not have comdat, and COFF linkers may GC comdat constructors.

The benefit of this is a lot less __asan_init() calls: one per DSO
instead of one per TU. It's also necessary for the upcoming
gc-sections-for-globals change on Linux, where multiple references to
section start symbols trigger quadratic behaviour in gold linker.

This is a rebase of r298756.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299696 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 19:55:13 +00:00
Evgeniy Stepanov
fcc345974f [asan] Delay creation of asan ctor.
Create the constructor in the module pass.
This in needed for the GC-friendly globals change, where the constructor can be
put in a comdat  in some cases, but we don't know about that in the function
pass.

This is a rebase of r298731 which was reverted due to a false alarm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299695 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 19:55:09 +00:00
Peter Collingbourne
593fb7ed17 Bitcode: Do not create FNENTRYs for aliases of functions.
There doesn't seem to be any point in doing this.

Differential Revision: https://reviews.llvm.org/D31691

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299694 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 19:39:24 +00:00
Keno Fischer
93e3e80c72 [StripDeadDebugInfo] Drop dead CUs entirely
Summary:
Prior to this while it would delete the dead DIGlobalVariables, it would
leave dead DICompileUnits and everything referenced therefrom. For a bit
bitcode file with thousands of compile units those dead nodes easily
outnumbered the real ones. Clean that up.

Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D31720

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299692 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 19:26:22 +00:00
Yi Kong
dc9458d5a7 Revert "[ARM] Add Kryo to available targets"
This reverts commit 942d6e6f58bf7e63810dd7cbcbce1fdfa5ebc6d4.

Build breakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299689 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 19:16:14 +00:00
Nirav Dave
d4d2ab353e [SDAG] Fix visitAND optimization to deal with vector extract case again.
Summary:
Fix case elided by rL298920.

Fixes PR32545.

Reviewers: eli.friedman, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31759

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299688 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 19:05:41 +00:00
Daniel Berlin
a96ab41df7 NewGVN: This patch makes memory congruence work for all types of
memorydefs, not just stores.  Along the way, we audit and fixup issues
about how we were tracking memory leaders, and improve the verifier
to notice more memory congruency issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299682 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 18:52:50 +00:00
Yi Kong
942d6e6f58 [ARM] Add Kryo to available targets
Summary:
Host CPU detection now supports Kryo, so we need to recognize it in ARM
target.

Reviewers: mcrosier, t.p.northover, rengolin, echristo, srhines

Reviewed By: t.p.northover, echristo

Subscribers: aemerson

Differential Revision: https://reviews.llvm.org/D31775

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299674 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 18:10:08 +00:00
Craig Topper
864291860e [InstSimplify] Teach SimplifyMulInst to recognize vectors of i1 as And. Not just scalar i1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299665 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 17:33:37 +00:00
Stanislav Mekhanoshin
3b10e5fb8d [AMDGPU] Eliminate barrier if workgroup size is not greater than wavefront size
If a workgroup size is known to be not greater than wavefront size
the s_barrier instruction is not needed since all threads are guarantied
to come to the same point at the same time.

Differential Revision: https://reviews.llvm.org/D31731

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299659 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 16:48:30 +00:00
Sam Kolton
3481b0868e [AMDGPU] Resubmit SDWA peephole: enable by default
Reviewers: vpykhtin, rampitec, arsenm

Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D31671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299654 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 15:03:28 +00:00
Simon Pilgrim
ed65bfc6c9 [X86][MMX] Test showing failure to create MMX non-temporal store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299640 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 10:32:30 +00:00
David Green
3b23ff5204 [ARM] Remove a dead ADD during the creation of TBBs
During the optimisation of jump tables in the constant island pass,
an extra ADD could be left over, now dead but not removed.

Differential Revision: https://reviews.llvm.org/D31389



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299634 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 08:32:47 +00:00
Craig Topper
3c3df0d82a [InstSimplify] Add test cases for mixing add/sub i1 with xor of i1. Seems we can simplify in one direction but not the other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299627 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 05:48:06 +00:00
Craig Topper
1194a001b6 [InstSimplify] Teach SimplifyAddInst and SimplifySubInst that vectors of i1 can be treated as Xor too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299626 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 05:28:41 +00:00
Keno Fischer
15bfd0f9a0 [X86 TTI] Implement LSV hook
Summary:
LSV wants to know the maximum size that can be loaded to a vector register.
On X86, this always matches the maximum register width. Implement this
accordingly and add a test to make sure that LSV can vectorize up to the
maximum permissible width on X86.

Reviewers: delena, arsenm

Reviewed By: arsenm

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D31504

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299589 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 20:51:38 +00:00
Ivan Krasin
f836c7dbde Revert r299536. [AMDGPU] SDWA peephole: enable by default.
Reason: breaks multiple bots:

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/3988
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/1173

Original Review URL: https://reviews.llvm.org/D31671



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299583 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 19:58:12 +00:00
Krzysztof Parzyszek
acdd13502c [Hexagon] Use -mattr to select HVX mode in a testcase, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299582 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 19:46:37 +00:00
Adam Nemet
c0a481413e [DAGCombine] Support FMF contract in fused multiple-and-sub too
This is a follow-on to r299096 which added support for fmadd.

Subtract does not have the case where with two multiply operands we commute in
order to fuse with the multiply with the fewer uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299572 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 17:58:48 +00:00
Sanjay Patel
bcca3be4b5 [InstCombine] add fold for icmp with or mask of low bits (PR32542)
We already have these 'and' folds:

// X & -C == -C -> X >  u ~C
// X & -C != -C -> X <= u ~C
//   iff C is a power of 2

...but we were missing the 'or' siblings.

http://rise4fun.com/Alive/n6

This should improve:
https://bugs.llvm.org/show_bug.cgi?id=32524
...but there are 2 or more other pieces to fix still.

Differential Revision: https://reviews.llvm.org/D31712



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299570 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 17:57:05 +00:00
Dmitry Preobrazhensky
4b7a5e5aa1 [AMDGPU][MC] Fix for Bug 28158 + LIT tests
Added support of the following instructions:
- s_cbranch_cdbgsys
- s_cbranch_cdbgsys_and_user
- s_cbranch_cdbgsys_or_user
- s_cbranch_cdbguser
- s_setkill

Reviewers: vpykhtin

Differential Revision: https://reviews.llvm.org/D31469

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299567 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 17:26:45 +00:00
Renato Golin
9331ebeba7 [ARM] Try to re-enable MachineBranchProb.ll for ARM/AArch64
Commit r298799 changed code that made the XFAIL on MachineBranchProb.ll
irrelevant, but some configurations still failed. I can't reproduce it
locally, so I'm hoping that enabling this will tell me if some
configurations will really fail or if they were just too slow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299558 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 16:27:11 +00:00
Sanjay Patel
81a71c4756 [InstCombine] add tests for missing icmp fold (PR32524)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299557 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 16:21:38 +00:00
Dmitry Preobrazhensky
8067b87e5f [AMDGPU][MC] Fix for Bug 28167 + LIT tests
Corrected src0 for v_writelane_b32:
- Enabled inline constants and literals for SI/CI (VOP2)
- Enabled inline constants for VI (VOP3)

Reviewers: vpykhtin, arsenm

https://reviews.llvm.org/D31463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299555 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 16:08:21 +00:00
Nirav Dave
af1205bfae [SystemZ] Prevent Merging Bitcast with non-normal loads
Fixes PR32505.

Reviewers: uweigand, jonpa

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31609

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299552 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 15:42:48 +00:00
Davide Italiano
6edf98cd9d [llvm-ar] errors go on stderr and not on stdout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299548 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 14:52:17 +00:00
Davide Italiano
4561efc963 [yaml2obj] Improve error message when output file cannot be opened.
Patch by Sam Clegg!

Differential Revision:  https://reviews.llvm.org/D31351

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299546 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 14:44:00 +00:00
Matthew Simpson
a9eefb0375 [LV] Make test case more robust
This test case depends on the loop being vectorized without forcing the
vectorization factor. If the profitability ever changes in the future (due to
cost model improvements), the test may no longer work as intended. Instead of
checking the resulting IR, we should just check the instruction costs. The
costs will be computed regardless if vectorization is profitable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299545 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 14:34:13 +00:00
Sanjay Patel
a070c921e5 [DAGCombiner] add and use TLI hook to convert and-of-seteq / or-of-setne to bitwise logic+setcc (PR32401)
This is a generic combine enabled via target hook to reduce icmp logic as discussed in:
https://bugs.llvm.org/show_bug.cgi?id=32401

It's likely that other targets will want to enable this hook for scalar transforms, 
and there are probably other patterns that can use bitwise logic to reduce comparisons.

Note that we are missing an IR canonicalization for these patterns, and we will probably
prefer the pair-of-compares form in IR (shorter, more likely to fold).

Differential Revision: https://reviews.llvm.org/D31483



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299542 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 14:09:39 +00:00
Jonas Paulsson
4a035b600a [DAGCombiner] Don't make a BUILD_VECTOR with operands of illegal type.
When DAGCombiner visits a SIGN_EXTEND_INREG of a BUILD_VECTOR with
constant operands, a new BUILD_VECTOR node will be created transformed
constants.

Llvm-stress found a case where the new BUILD_VECTOR had constant operands
of an illegal type, because the (legal) element type is in fact not a legal
scalar type.

This patch changes this so that the new BUILD_VECTOR has the same operand
type as the old one.

Review: Eli Friedman, Nirav Dave
https://bugs.llvm.org//show_bug.cgi?id=32422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299540 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 13:45:37 +00:00
Sanjay Patel
0a06935a2e [InstCombine] add tests for missing add canonicalization; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299539 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 13:33:10 +00:00
Daniel Sanders
be2d374747 [globalisel][tablegen] Fix patterns involving multiple ComplexPatterns.
Summary:
Temporaries are now allocated to operands instead of predicates and this
allocation is used to correctly pair up the rendered operands with the
matched operands.

Previously, ComplexPatterns were allocated temporaries independently in the
Src Pattern and Dst Pattern, leading to mismatches. Additionally, the Dst
Pattern failed to account for the allocated index and therefore always used
temporary 0, 1, ... when it should have used base+0, base+1, ...

Thanks to Aditya Nandakumar for noticing the bug.

Depends on D30539

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: rovka

Subscribers: igorb, dberris, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D31054

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299538 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 13:14:03 +00:00