Commit Graph

9955 Commits

Author SHA1 Message Date
Dan Gohman
ff26d4e9ce Teach lint how to look through simple store+load pairs and other
effective no-op constructs, to make it more effective on
unoptimized IR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 16:21:24 +00:00
Dan Gohman
05d6253727 Teach instcombine to promote alloca array sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 15:09:00 +00:00
Dan Gohman
8496d50412 Add a testcase for getelementptr index promotion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 15:07:59 +00:00
Dan Gohman
292fc87fe2 Add a lint check for returning the address of stack memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 04:33:42 +00:00
Dan Gohman
f75a7d3fbf Eliminate the restriction that the array size in an alloca must be i32.
This will help reduce the amount of casting required on 64-bit targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 01:14:11 +00:00
Jakob Stoklund Olesen
700bfada63 Add a -regalloc=default option that chooses a register allocator based on the -O
optimization level.

This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 23:57:25 +00:00
Evan Cheng
84f60b7359 llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 22:08:38 +00:00
Kevin Enderby
bd658918df MC/X86: Add aliases for Jcc variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 21:33:19 +00:00
Devang Patel
d8720f4ba3 Do not drop location info for inlined function args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104884 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 20:25:04 +00:00
Stuart Hastings
57041b6f33 Adjust test case for lexical block pruning. Follow-on to r104842 and Radar 7424645.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104876 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 19:57:51 +00:00
Devang Patel
57bd643113 Let's try one more time to match patterns.
The goal is to match following 3 lines. In otherwords, a temp. label between to DEBUG_VALUE comments.
        ;DEBUG_VALUE: bar:x <- undef   ## 2010-01-18-Inlined-Debug.c:7
Ltmp1:
        ;DEBUG_VALUE: foo:__x <- undef ## 2010-01-18-Inlined-Debug.c:5



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104872 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 19:46:38 +00:00
Duncan Sands
1d9b973fd7 Teach instCombine to remove malloc+free if malloc's only uses are comparisons
to null.  Patch by Matti Niemenmaa.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104871 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 19:09:06 +00:00
Devang Patel
895f2dfd45 Temp. labels number may not match for all configurations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 17:51:08 +00:00
Devang Patel
55e9717e59 inlined function's arguments need a label to mark the start point because they are not directly attached to current function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 16:47:30 +00:00
Stuart Hastings
aa66d2f48a Support for nested functions/classes in debug output. Radar 7424645.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104841 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 16:16:54 +00:00
Gabor Greif
2893a460d8 rename test to represent meaningful date
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 09:32:38 +00:00
Bob Wilson
cdef41a6b4 Add a test for llvm-gcc svn r104726.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 05:30:36 +00:00
Eric Christopher
bd3ba537cd Add a quick test of relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 00:53:40 +00:00
Devang Patel
80250686d5 Simplify. Eliminate unneeded debug_loc entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104785 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 23:55:23 +00:00
Dan Gohman
882ddb492d Reinstate checking of stackrestore, with checking for both Read
and Write, and add a comment explaining this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 22:21:25 +00:00
Dan Gohman
113b3e2c6e Implement checking of the tail keyword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:46:36 +00:00
Devang Patel
394427b014 Update debug info when live-in reg is copied into a vreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:18:50 +00:00
Kevin Enderby
b106543592 Fix the x86 move to/from segment register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:10:45 +00:00
Dale Johannesen
b09e793bf9 Testcase for 104624/104619/PR7191/8023512.
Reduced from one provided by Duncan Sands, thanks!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:55:45 +00:00
Devang Patel
c3f5f783a2 First cut at supporting .debug_loc section.
This is used to track variable information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104649 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 23:40:22 +00:00
Benjamin Kramer
48aefe15d0 Properly promote operands when optimizing a single-character memcmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 22:53:43 +00:00
Eric Christopher
02b46bc942 Add support for initialized global data for darwin tls. Update comments
and testcases accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:28:50 +00:00
Kevin Enderby
cf50a5390c Changed the encoding of X86 floating point stack operations where both operands
are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 20:52:34 +00:00
Dale Johannesen
854f30d965 Removing test; Chris thinks it's better to have the
bug go untested than have a testcase this large.  So be it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104632 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 20:40:10 +00:00
Daniel Dunbar
39e2dd7bab MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:32 +00:00
Dale Johannesen
86234c30a7 Fix another variant of PR 7191. Also add a testcase
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104624 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:47:23 +00:00
Daniel Dunbar
79373680ed MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:40:53 +00:00
Kevin Enderby
04ac770be9 The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
for the 64-bit version of the Bit Test instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:16:58 +00:00
Eric Christopher
7e2f5aaa67 Make sure aeskeygenassist uses an unsigned immediate field.
Fixes rdar://8017638


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:33:22 +00:00
Dan Gohman
e350690e3b Fix an mmx movd encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:51:08 +00:00
Kevin Enderby
ca956dc0f6 MC/X86: Add aliases for CMOVcc variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:32:23 +00:00
Bob Wilson
bb7ecb2bf5 Thumb2 RSBS instructions were being printed without the 'S' suffix.
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:44:06 +00:00
Evan Cheng
c7cf10c97e LR is in GPR, not tGPR even in Thumb1 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:00:18 +00:00
Daniel Dunbar
62e4c671b6 MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
4c361972fd MC/X86: Add alias for setz, setnz, jz, jnz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 06:37:33 +00:00
Evan Cheng
2457f2c661 Implement @llvm.returnaddress. rdar://8015977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:47:14 +00:00
Eric Christopher
1e6d3ac709 This test is darwin only. Make it so(tm).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104418 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:55:55 +00:00
Bob Wilson
be751cfe9c Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:23:12 +00:00
Eric Christopher
8116ca5134 Add full bss data support for darwin tls variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104414 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:10:22 +00:00
Kevin Enderby
9d31d79493 Added retl for 32-bit x86 and added retq for 64-bit x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:01:38 +00:00
Bob Wilson
78f006acdf Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 21:05:32 +00:00
Chris Lattner
a26a8471bd now that fp reg kill insertion stuff happens as a separate
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 18:17:54 +00:00
Jakob Stoklund Olesen
2afb7505c5 Teach VirtRegRewriter to handle spilling in instructions that have multiple
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 16:36:13 +00:00
Dale Johannesen
7d07b48b26 Fix i64->f64 conversion, x86-64, -no-sse. A bit
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:52:33 +00:00
Evan Cheng
f7d87ee158 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:43:17 +00:00