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914f2ff9e6
InlineSpiller inserts loads and spills immediately instead of deferring to VirtRegMap. This is possible now because SlotIndexes allows instructions to be inserted and renumbered. This is work in progress, and is mostly a copy of TrivialSpiller so far. It works very well for functions that don't require spilling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107227 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
1.8 KiB
CMake
82 lines
1.8 KiB
CMake
add_llvm_library(LLVMCodeGen
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AggressiveAntiDepBreaker.cpp
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Analysis.cpp
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BranchFolding.cpp
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CalcSpillWeights.cpp
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CodePlacementOpt.cpp
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CriticalAntiDepBreaker.cpp
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DeadMachineInstructionElim.cpp
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DwarfEHPrepare.cpp
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ELFCodeEmitter.cpp
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ELFWriter.cpp
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GCMetadata.cpp
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GCMetadataPrinter.cpp
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GCStrategy.cpp
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IfConversion.cpp
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InlineSpiller.cpp
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IntrinsicLowering.cpp
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LLVMTargetMachine.cpp
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LatencyPriorityQueue.cpp
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LiveInterval.cpp
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LiveIntervalAnalysis.cpp
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LiveStackAnalysis.cpp
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LiveVariables.cpp
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LowerSubregs.cpp
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MachineBasicBlock.cpp
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MachineCSE.cpp
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MachineDominators.cpp
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MachineFunction.cpp
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MachineFunctionAnalysis.cpp
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MachineFunctionPass.cpp
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MachineFunctionPrinterPass.cpp
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MachineInstr.cpp
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MachineLICM.cpp
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MachineLoopInfo.cpp
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MachineModuleInfo.cpp
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MachineModuleInfoImpls.cpp
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MachinePassRegistry.cpp
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MachineRegisterInfo.cpp
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MachineSSAUpdater.cpp
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MachineSink.cpp
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MachineVerifier.cpp
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ObjectCodeEmitter.cpp
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OcamlGC.cpp
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OptimizeExts.cpp
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OptimizePHIs.cpp
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PHIElimination.cpp
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Passes.cpp
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PostRAHazardRecognizer.cpp
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PostRASchedulerList.cpp
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PreAllocSplitting.cpp
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ProcessImplicitDefs.cpp
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PrologEpilogInserter.cpp
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PseudoSourceValue.cpp
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RegAllocFast.cpp
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RegAllocLinearScan.cpp
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RegAllocPBQP.cpp
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RegisterCoalescer.cpp
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RegisterScavenging.cpp
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ScheduleDAG.cpp
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ScheduleDAGEmit.cpp
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ScheduleDAGInstrs.cpp
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ScheduleDAGPrinter.cpp
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ShadowStackGC.cpp
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ShrinkWrapping.cpp
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SimpleRegisterCoalescing.cpp
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SjLjEHPrepare.cpp
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SlotIndexes.cpp
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Spiller.cpp
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StackProtector.cpp
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StackSlotColoring.cpp
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StrongPHIElimination.cpp
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TailDuplication.cpp
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TargetInstrInfoImpl.cpp
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TargetLoweringObjectFileImpl.cpp
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TwoAddressInstructionPass.cpp
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UnreachableBlockElim.cpp
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VirtRegMap.cpp
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VirtRegRewriter.cpp
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)
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target_link_libraries (LLVMCodeGen LLVMCore LLVMScalarOpts)
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