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llvm/test/CodeGen/NVPTX
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Justin Lebar dd9e8b3bcc [NVPTX] Add intrinsics for shfl instructions. 
Summary:
Currently clang emits these instructions via inline (volatile) asm in
the CUDA headers.  Switching to intrinsics will let the optimizer reason
across calls to these intrinsics.

Reviewers: tra

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D21160

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272298 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-09 20:04:08 +00:00
..
access-non-generic.ll
[NVPTX] Adds a new address space inference pass.
2016-03-20 20:59:20 +00:00
add-128bit.ll
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addrspacecast-gvar.ll
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addrspacecast.ll
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aggr-param.ll
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alias.ll
[CUDA] Die gracefully when trying to output an LLVM alias.
2016-01-23 21:12:20 +00:00
annotations.ll
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arg-lowering.ll
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arithmetic-fp-sm20.ll
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arithmetic-int.ll
[NVPTX] expand mul_lohi to mul_lo and mul_hi
2016-01-22 19:47:26 +00:00
atomics.ll
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bfe.ll
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branch-fold.ll
Roll forward r242871
2015-07-29 18:59:09 +00:00
bug17709.ll
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bug21465.ll
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bug22246.ll
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bug22322.ll
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bug26185-2.ll
[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection
2016-05-02 18:12:02 +00:00
bug26185.ll
[NVPTX] Handle ldg created from sign-/zero-extended load
2016-04-05 12:38:01 +00:00
bypass-div.ll
Use 32-bit divides instead of 64-bit divides where possible.
2015-08-11 22:16:34 +00:00
call-with-alloca-buffer.ll
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callchain.ll
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calling-conv.ll
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combine-min-max.ll
[NVPTX] Let NVPTX backend detect integer min and max patterns.
2015-08-26 23:22:02 +00:00
compare-int.ll
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constant-vectors.ll
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convergent-mir-call.ll
[NVPTX] Use different, convergent MIs for convergent calls.
2016-03-01 19:24:03 +00:00
convert-fp.ll
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convert-int-sm20.ll
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ctlz.ll
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ctpop.ll
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cttz.ll
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debug-file-loc.ll
[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
2016-04-15 15:57:41 +00:00
disable-opt.ll
[NVPTX] Disable performance optimizations when OptLevel==None
2016-02-04 04:15:36 +00:00
div-ri.ll
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envreg.ll
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extloadv.ll
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fast-math.ll
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fma-assoc.ll
SelectionDAG: Prefer to combine multiplication with less uses for fma
2015-08-11 19:21:46 +00:00
fma-disable.ll
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fma.ll
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fp16.ll
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fp-contract.ll
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fp-literals.ll
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function-align.ll
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generic-to-nvvm.ll
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global-addrspace.ll
[NVPTX] Allow undef value as global initializer
2015-08-22 05:40:26 +00:00
global-ctor-empty.ll
[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
2016-01-30 01:07:38 +00:00
global-ctor.ll
[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
2016-01-30 01:07:38 +00:00
global-dtor.ll
[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
2016-01-30 01:07:38 +00:00
global-ordering.ll
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global-visibility.ll
[NVPTX] Do not emit .hidden or .protected directives as they are not allowed by PTX.
2016-01-15 23:57:53 +00:00
globals_init.ll
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globals_lowering.ll
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gvar-init.ll
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half.ll
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i1-global.ll
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i1-int-to-fp.ll
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i1-param.ll
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i8-param.ll
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imad.ll
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implicit-def.ll
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inline-asm.ll
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intrin-nocapture.ll
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intrinsic-old.ll
[NVPTX] Added NVVMIntrRange pass
2016-05-26 17:02:56 +00:00
intrinsics.ll
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isspacep.ll
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ld-addrspace.ll
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ld-generic.ll
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ldparam-v4.ll
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ldu-i8.ll
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ldu-ldg.ll
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ldu-reg-plus-offset.ll
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lit.local.cfg
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load-sext-i1.ll
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load-with-non-coherent-cache.ll
[NVPTX] Use LDG for pointer induction variables.
2015-08-05 23:11:57 +00:00
local-stack-frame.ll
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loop-vectorize.ll
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lower-aggr-copies.ll
Revert "Change memcpy/memset/memmove to have dest and source alignments."
2015-11-19 05:56:52 +00:00
lower-alloca.ll
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lower-kernel-ptr-arg.ll
[NVPTX] convert pointers in byval kernel arguments to global
2015-07-31 21:44:14 +00:00
machine-sink.ll
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MachineSink-call.ll
[NVPTX] Annotate call machine instructions as calls.
2016-02-17 17:46:50 +00:00
MachineSink-convergent.ll
[NVPTX] Test that MachineSink won't sink across llvm.cuda.syncthreads.
2016-02-17 17:46:52 +00:00
managed.ll
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misaligned-vector-ldst.ll
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module-inline-asm.ll
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mulwide.ll
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noduplicate-syncthreads.ll
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nounroll.ll
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nvcl-param-align.ll
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nvvm-reflect-module-flag.ll
[NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect.
2016-04-01 01:09:07 +00:00
nvvm-reflect.ll
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param-align.ll
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pr13291-i1-store.ll
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pr16278.ll
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pr17529.ll
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refl1.ll
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reg-copy.ll
[NVPTX] allow register copy between float and int
2015-08-01 18:02:12 +00:00
rotate.ll
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rsqrt.ll
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sched1.ll
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sched2.ll
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sext-in-reg.ll
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sext-params.ll
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shfl.ll
[NVPTX] Add intrinsics for shfl instructions.
2016-06-09 20:04:08 +00:00
shift-parts.ll
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simple-call.ll
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sm-version-20.ll
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sm-version-21.ll
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sm-version-30.ll
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sm-version-32.ll
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sm-version-35.ll
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sm-version-37.ll
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sm-version-50.ll
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sm-version-52.ll
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sm-version-53.ll
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speculative-execution-divergent-target.ll
Move divergent-target test into CodeGen/NVPTX because it requires an NVPTX target.
2016-04-15 01:20:52 +00:00
st-addrspace.ll
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st-generic.ll
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surf-read-cuda.ll
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surf-read.ll
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surf-write-cuda.ll
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surf-write.ll
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symbol-naming.ll
Have a single way for creating unique value names.
2015-11-22 00:16:24 +00:00
TailDuplication-convergent.ll
Don't tail-duplicate blocks that contain convergent instructions.
2016-02-22 17:50:52 +00:00
tex-read-cuda.ll
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tex-read.ll
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texsurf-queries.ll
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tuple-literal.ll
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vec8.ll
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vec-param-load.ll
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vector-args.ll
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vector-call.ll
Fix a bunch of trivial cases of 'CHECK[^:]*$' in the tests. NFCI
2015-08-10 19:01:27 +00:00
vector-compare.ll
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vector-global.ll
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vector-loads.ll
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vector-return.ll
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vector-select.ll
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vector-stores.ll
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weak-global.ll
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weak-linkage.ll
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