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https://github.com/RPCSX/llvm.git
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bd5e5e1e49
In r260133, LLVM was changed to no longer extend i8/i16 return values, as it's not required by the ABI. However, code was found in the wild that relies on the old behaviour on Darwin, so this commit reverts back to that old behaviour for Darwin. On other platforms, it's less likely that code would be depending on the old behaviour, as GCC and MSVC haven't been extending such return values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261235 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
2.8 KiB
LLVM
120 lines
2.8 KiB
LLVM
; RUN: llc -march=x86-64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-64
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; RUN: llc -march=x86 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-32
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.10.0"
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define zeroext i8 @test_udivrem_zext_ah(i8 %x, i8 %y) {
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; CHECK-LABEL: test_udivrem_zext_ah
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; CHECK: divb
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; CHECK: movzbl %ah, [[REG_REM:%[a-z0-9]+]]
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; CHECK: movb %al, ([[REG_ZPTR:%[a-z0-9]+]])
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; CHECK: movl [[REG_REM]], %eax
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; CHECK: ret
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%div = udiv i8 %x, %y
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store i8 %div, i8* @z
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%1 = urem i8 %x, %y
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ret i8 %1
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}
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define zeroext i8 @test_urem_zext_ah(i8 %x, i8 %y) {
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; CHECK-LABEL: test_urem_zext_ah
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; CHECK: divb
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; CHECK: movzbl %ah, %eax
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; CHECK: ret
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%1 = urem i8 %x, %y
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ret i8 %1
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}
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define i8 @test_urem_noext_ah(i8 %x, i8 %y) {
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; CHECK-LABEL: test_urem_noext_ah
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; CHECK: divb [[REG_X:%[a-z0-9]+]]
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; CHECK: movzbl %ah, %eax
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; CHECK: addb [[REG_X]], %al
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; CHECK: ret
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%1 = urem i8 %x, %y
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%2 = add i8 %1, %y
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ret i8 %2
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}
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define i64 @test_urem_zext64_ah(i8 %x, i8 %y) {
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; CHECK-LABEL: test_urem_zext64_ah
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; CHECK: divb
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; CHECK: movzbl %ah, %eax
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; CHECK-32: xorl %edx, %edx
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; CHECK: ret
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%1 = urem i8 %x, %y
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%2 = zext i8 %1 to i64
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ret i64 %2
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}
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define signext i8 @test_sdivrem_sext_ah(i8 %x, i8 %y) {
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; CHECK-LABEL: test_sdivrem_sext_ah
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; CHECK: cbtw
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; CHECK: idivb
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; CHECK: movsbl %ah, [[REG_REM:%[a-z0-9]+]]
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; CHECK: movb %al, ([[REG_ZPTR]])
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; CHECK: movl [[REG_REM]], %eax
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; CHECK: ret
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%div = sdiv i8 %x, %y
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store i8 %div, i8* @z
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%1 = srem i8 %x, %y
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ret i8 %1
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}
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define signext i8 @test_srem_sext_ah(i8 %x, i8 %y) {
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; CHECK-LABEL: test_srem_sext_ah
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; CHECK: cbtw
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; CHECK: idivb
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; CHECK: movsbl %ah, %eax
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; CHECK: ret
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%1 = srem i8 %x, %y
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ret i8 %1
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}
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define i8 @test_srem_noext_ah(i8 %x, i8 %y) {
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; CHECK-LABEL: test_srem_noext_ah
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; CHECK: cbtw
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; CHECK: idivb [[REG_X:%[a-z0-9]+]]
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; CHECK: movsbl %ah, %eax
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; CHECK: addb [[REG_X]], %al
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; CHECK: ret
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%1 = srem i8 %x, %y
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%2 = add i8 %1, %y
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ret i8 %2
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}
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define i64 @test_srem_sext64_ah(i8 %x, i8 %y) {
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; CHECK-LABEL: test_srem_sext64_ah
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; CHECK: cbtw
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; CHECK: idivb
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; CHECK: movsbl %ah, %eax
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; CHECK-32: movl %eax, %edx
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; CHECK-32: sarl $31, %edx
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; CHECK-64: movsbq %al, %rax
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; CHECK: ret
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%1 = srem i8 %x, %y
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%2 = sext i8 %1 to i64
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ret i64 %2
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}
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define i64 @pr25754(i8 %a, i8 %c) {
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; CHECK-LABEL: pr25754
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; CHECK: movzbl {{.+}}, %eax
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; CHECK: divb
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; CHECK: movzbl %ah, %ecx
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; CHECK: movzbl %al, %eax
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; CHECK-32: addl %ecx, %eax
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; CHECK-32: sbbl %edx, %edx
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; CHECK-32: andl $1, %edx
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; CHECK-64: addq %rcx, %rax
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; CHECK: ret
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%r1 = urem i8 %a, %c
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%d1 = udiv i8 %a, %c
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%r2 = zext i8 %r1 to i64
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%d2 = zext i8 %d1 to i64
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%ret = add i64 %r2, %d2
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ret i64 %ret
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}
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@z = external global i8
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