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These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
452 lines
14 KiB
C++
452 lines
14 KiB
C++
//===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Cell SPU implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SPUInstrInfo.h"
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#include "SPUInstrBuilder.h"
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#include "SPUTargetMachine.h"
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#include "SPUHazardRecognizers.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#define GET_INSTRINFO_CTOR
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#include "SPUGenInstrInfo.inc"
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using namespace llvm;
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namespace {
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//! Predicate for an unconditional branch instruction
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inline bool isUncondBranch(const MachineInstr *I) {
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unsigned opc = I->getOpcode();
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return (opc == SPU::BR
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|| opc == SPU::BRA
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|| opc == SPU::BI);
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}
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//! Predicate for a conditional branch instruction
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inline bool isCondBranch(const MachineInstr *I) {
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unsigned opc = I->getOpcode();
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return (opc == SPU::BRNZr32
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|| opc == SPU::BRNZv4i32
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|| opc == SPU::BRZr32
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|| opc == SPU::BRZv4i32
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|| opc == SPU::BRHNZr16
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|| opc == SPU::BRHNZv8i16
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|| opc == SPU::BRHZr16
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|| opc == SPU::BRHZv8i16);
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}
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}
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SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
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: SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
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TM(tm),
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RI(*TM.getSubtargetImpl(), *this)
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{ /* NOP */ }
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/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
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/// this target when scheduling the DAG.
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ScheduleHazardRecognizer *SPUInstrInfo::CreateTargetHazardRecognizer(
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const TargetMachine *TM,
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const ScheduleDAG *DAG) const {
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const TargetInstrInfo *TII = TM->getInstrInfo();
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assert(TII && "No InstrInfo?");
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return new SPUHazardRecognizer(*TII);
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}
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unsigned
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SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SPU::LQDv16i8:
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case SPU::LQDv8i16:
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case SPU::LQDv4i32:
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case SPU::LQDv4f32:
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case SPU::LQDv2f64:
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case SPU::LQDr128:
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case SPU::LQDr64:
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case SPU::LQDr32:
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case SPU::LQDr16: {
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const MachineOperand MOp1 = MI->getOperand(1);
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const MachineOperand MOp2 = MI->getOperand(2);
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if (MOp1.isImm() && MOp2.isFI()) {
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FrameIndex = MOp2.getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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}
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return 0;
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}
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unsigned
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SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SPU::STQDv16i8:
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case SPU::STQDv8i16:
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case SPU::STQDv4i32:
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case SPU::STQDv4f32:
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case SPU::STQDv2f64:
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case SPU::STQDr128:
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case SPU::STQDr64:
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case SPU::STQDr32:
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case SPU::STQDr16:
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case SPU::STQDr8: {
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const MachineOperand MOp1 = MI->getOperand(1);
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const MachineOperand MOp2 = MI->getOperand(2);
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if (MOp1.isImm() && MOp2.isFI()) {
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FrameIndex = MOp2.getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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}
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return 0;
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}
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void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const
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{
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// We support cross register class moves for our aliases, such as R3 in any
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// reg class to any other reg class containing R3. This is required because
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// we instruction select bitconvert i64 -> f64 as a noop for example, so our
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// types have no specific meaning.
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BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void
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SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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{
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unsigned opc;
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bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
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if (RC == SPU::GPRCRegisterClass) {
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opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
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} else if (RC == SPU::R64CRegisterClass) {
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opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
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} else if (RC == SPU::R64FPRegisterClass) {
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opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
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} else if (RC == SPU::R32CRegisterClass) {
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opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
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} else if (RC == SPU::R32FPRegisterClass) {
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opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
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} else if (RC == SPU::R16CRegisterClass) {
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opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
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} else if (RC == SPU::R8CRegisterClass) {
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opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
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} else if (RC == SPU::VECREGRegisterClass) {
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opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
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} else {
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llvm_unreachable("Unknown regclass!");
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}
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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addFrameReference(BuildMI(MBB, MI, DL, get(opc))
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.addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
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}
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void
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SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const
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{
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unsigned opc;
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bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
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if (RC == SPU::GPRCRegisterClass) {
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opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
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} else if (RC == SPU::R64CRegisterClass) {
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opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
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} else if (RC == SPU::R64FPRegisterClass) {
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opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
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} else if (RC == SPU::R32CRegisterClass) {
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opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
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} else if (RC == SPU::R32FPRegisterClass) {
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opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
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} else if (RC == SPU::R16CRegisterClass) {
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opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
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} else if (RC == SPU::R8CRegisterClass) {
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opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
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} else if (RC == SPU::VECREGRegisterClass) {
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opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
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} else {
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llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
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}
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
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}
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//! Branch analysis
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/*!
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\note This code was kiped from PPC. There may be more branch analysis for
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CellSPU than what's currently done here.
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*/
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bool
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SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isUnpredicatedTerminator(I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (isUncondBranch(LastInst)) {
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// Check for jump tables
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if (!LastInst->getOperand(0).isMBB())
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return true;
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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} else if (isCondBranch(LastInst)) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(1).getMBB();
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DEBUG(errs() << "Pushing LastInst: ");
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DEBUG(LastInst->dump());
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Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
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Cond.push_back(LastInst->getOperand(0));
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return false;
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}
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// Otherwise, don't know what this is.
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return true;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with a conditional and unconditional branch, handle it.
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if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
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TBB = SecondLastInst->getOperand(1).getMBB();
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DEBUG(errs() << "Pushing SecondLastInst: ");
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DEBUG(SecondLastInst->dump());
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Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
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Cond.push_back(SecondLastInst->getOperand(0));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The second
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// one is not executed, so remove it.
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if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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// search MBB for branch hint labels and branch hit ops
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static void removeHBR( MachineBasicBlock &MBB) {
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I){
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if (I->getOpcode() == SPU::HBRA ||
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I->getOpcode() == SPU::HBR_LABEL){
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I=MBB.erase(I);
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}
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}
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}
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unsigned
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SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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removeHBR(MBB);
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if (I == MBB.begin())
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return 0;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return 0;
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--I;
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}
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if (!isCondBranch(I) && !isUncondBranch(I))
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return 0;
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// Remove the first branch.
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DEBUG(errs() << "Removing branch: ");
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DEBUG(I->dump());
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin())
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return 1;
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--I;
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if (!(isCondBranch(I) || isUncondBranch(I)))
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return 1;
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// Remove the second branch.
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DEBUG(errs() << "Removing second branch: ");
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DEBUG(I->dump());
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I->eraseFromParent();
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return 2;
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}
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/** Find the optimal position for a hint branch instruction in a basic block.
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* This should take into account:
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* -the branch hint delays
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* -congestion of the memory bus
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* -dual-issue scheduling (i.e. avoid insertion of nops)
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* Current implementation is rather simplistic.
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*/
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static MachineBasicBlock::iterator findHBRPosition(MachineBasicBlock &MBB)
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{
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MachineBasicBlock::iterator J = MBB.end();
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for( int i=0; i<8; i++) {
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if( J == MBB.begin() ) return J;
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J--;
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}
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return J;
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}
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unsigned
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SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"SPU branch conditions have two components!");
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MachineInstrBuilder MIB;
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//TODO: make a more accurate algorithm.
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bool haveHBR = MBB.size()>8;
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removeHBR(MBB);
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MCSymbol *branchLabel = MBB.getParent()->getContext().CreateTempSymbol();
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// Add a label just before the branch
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if (haveHBR)
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MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
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// One-way branch.
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if (FBB == 0) {
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if (Cond.empty()) {
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// Unconditional branch
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MIB = BuildMI(&MBB, DL, get(SPU::BR));
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MIB.addMBB(TBB);
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DEBUG(errs() << "Inserted one-way uncond branch: ");
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DEBUG((*MIB).dump());
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// basic blocks have just one branch so it is safe to add the hint a its
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if (haveHBR) {
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MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
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MIB.addSym(branchLabel);
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MIB.addMBB(TBB);
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}
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} else {
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// Conditional branch
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MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
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MIB.addReg(Cond[1].getReg()).addMBB(TBB);
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if (haveHBR) {
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MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
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MIB.addSym(branchLabel);
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MIB.addMBB(TBB);
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}
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DEBUG(errs() << "Inserted one-way cond branch: ");
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DEBUG((*MIB).dump());
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}
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return 1;
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} else {
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MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
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MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
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// Two-way Conditional Branch.
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MIB.addReg(Cond[1].getReg()).addMBB(TBB);
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MIB2.addMBB(FBB);
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if (haveHBR) {
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MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
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MIB.addSym(branchLabel);
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MIB.addMBB(FBB);
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}
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DEBUG(errs() << "Inserted conditional branch: ");
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DEBUG((*MIB).dump());
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DEBUG(errs() << "part 2: ");
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DEBUG((*MIB2).dump());
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return 2;
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}
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}
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//! Reverses a branch's condition, returning false on success.
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bool
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SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
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const {
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// Pretty brainless way of inverting the condition, but it works, considering
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// there are only two conditions...
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static struct {
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unsigned Opc; //! The incoming opcode
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unsigned RevCondOpc; //! The reversed condition opcode
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} revconds[] = {
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{ SPU::BRNZr32, SPU::BRZr32 },
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{ SPU::BRNZv4i32, SPU::BRZv4i32 },
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{ SPU::BRZr32, SPU::BRNZr32 },
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{ SPU::BRZv4i32, SPU::BRNZv4i32 },
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{ SPU::BRHNZr16, SPU::BRHZr16 },
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{ SPU::BRHNZv8i16, SPU::BRHZv8i16 },
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{ SPU::BRHZr16, SPU::BRHNZr16 },
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{ SPU::BRHZv8i16, SPU::BRHNZv8i16 }
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};
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unsigned Opc = unsigned(Cond[0].getImm());
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// Pretty dull mapping between the two conditions that SPU can generate:
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for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
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if (revconds[i].Opc == Opc) {
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Cond[0].setImm(revconds[i].RevCondOpc);
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return false;
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}
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}
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return true;
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}
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