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a703f676f7
Add support for resolving MIPS64r2 and MIPS64r6 relocations in MCJIT. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D9667 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238424 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.0 KiB
LLVM
37 lines
1.0 KiB
LLVM
; RUN: %lli -jit-kind=orc-mcjit -disable-lazy-compilation=false -relocation-model=pic -code-model=small %s
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; XFAIL: mips-, mipsel-, i686, i386, aarch64, arm
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define i32 @main() nounwind {
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entry:
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call void @lazily_compiled_address_is_consistent()
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ret i32 0
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}
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; Test PR3043: @test should have the same address before and after
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; it's JIT-compiled.
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@funcPtr = common global i1 ()* null, align 4
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@lcaic_failure = internal constant [46 x i8] c"@lazily_compiled_address_is_consistent failed\00"
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define void @lazily_compiled_address_is_consistent() nounwind {
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entry:
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store i1 ()* @test, i1 ()** @funcPtr
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%pass = tail call i1 @test() ; <i32> [#uses=1]
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br i1 %pass, label %pass_block, label %fail_block
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pass_block:
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ret void
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fail_block:
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call i32 @puts(i8* getelementptr([46 x i8], [46 x i8]* @lcaic_failure, i32 0, i32 0))
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call void @exit(i32 1)
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unreachable
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}
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define i1 @test() nounwind {
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entry:
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%tmp = load i1 ()*, i1 ()** @funcPtr
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%eq = icmp eq i1 ()* %tmp, @test
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ret i1 %eq
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}
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declare i32 @puts(i8*) noreturn
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declare void @exit(i32) noreturn
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