llvm/lib/CodeGen
Matt Arsenault 012b7077ca PEI: Skip dead objects when looking at CSRs
On AMDGPU if an SGPR is spilled to a VGPR, the frame index
is deleted. If there were any CSR SGPRs, this woudl
assert when setting the offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301961 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-02 18:56:28 +00:00
..
AsmPrinter [PDB/CodeView] Read/write codeview inlinee line information. 2017-05-02 16:56:09 +00:00
GlobalISel [globalisel][tablegen] Compute available feature bits correctly. 2017-04-29 17:30:09 +00:00
MIRParser MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFC 2017-05-01 22:32:25 +00:00
SelectionDAG [DAGCombine] (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry) 2017-05-02 14:15:48 +00:00
AggressiveAntiDepBreaker.cpp Resubmit r301309: [DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler. 2017-04-25 15:39:57 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp Move llvm::canBeOmittedFromSymbolTable() to Analysis. 2017-03-31 04:46:31 +00:00
AntiDepBreaker.h Resubmit r301309: [DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler. 2017-04-25 15:39:57 +00:00
AtomicExpandPass.cpp Rename AttributeSet to AttributeList 2017-03-21 16:57:19 +00:00
BasicTargetTransformInfo.cpp
BranchCoalescing.cpp Strip trailing whitespace. 2017-03-10 22:53:19 +00:00
BranchFolding.cpp CodeGen: BranchFolding: Merge identical blocks, even if they are short. 2017-04-10 22:28:12 +00:00
BranchFolding.h NFC: Reformats comments according to the coding guildelines. 2017-03-15 06:29:23 +00:00
BranchRelaxation.cpp Cleanup dump() functions. 2017-01-28 02:02:38 +00:00
BuiltinGCs.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-27 22:45:06 +00:00
CalcSpillWeights.cpp
CallingConvLower.cpp [CodeGen] Remove dead call-or-prologue enum from CCState 2017-02-02 21:58:22 +00:00
CMakeLists.txt MachineFrameInfo: Move implementation to an own file; NFC 2017-04-26 23:36:58 +00:00
CodeGen.cpp CodeGen.cpp: Sort alphabetically; NFC 2017-03-18 05:05:32 +00:00
CodeGenPrepare.cpp Rename WeakVH to WeakTrackingVH; NFC 2017-05-01 17:07:49 +00:00
CountingFunctionInserter.cpp Module::getOrInsertFunction is using C-style vararg instead of variadic templates. 2017-04-11 15:01:18 +00:00
CriticalAntiDepBreaker.cpp Resubmit r301309: [DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler. 2017-04-25 15:39:57 +00:00
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp Fix typos 2017-02-15 22:19:06 +00:00
DetectDeadLanes.cpp Spelling mistakes in comments. NFCI. 2017-03-30 12:59:53 +00:00
DFAPacketizer.cpp Remove unnecessary conditions as suggested by clang-tidy. NFC 2017-05-01 16:18:42 +00:00
DwarfEHPrepare.cpp
EarlyIfConversion.cpp
EdgeBundles.cpp
ExecutionDepsFix.cpp [ExecutionDepsFix] Don't recurse over the CFG 2017-04-05 17:42:56 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
FaultMaps.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-27 22:45:06 +00:00
FEntryInserter.cpp [X86] Implement -mfentry 2017-01-31 17:00:27 +00:00
FuncletLayout.cpp
GCMetadata.cpp
GCMetadataPrinter.cpp
GCRootLowering.cpp
GCStrategy.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-27 22:45:06 +00:00
GlobalMerge.cpp
IfConversion.cpp [IfConversion] Only renormalize probabilities if branches are analyzable 2017-03-06 19:12:42 +00:00
ImplicitNullChecks.cpp [INC] Test commit. NFC. 2017-04-12 04:41:35 +00:00
InlineSpiller.cpp PR32382: Fix emitting complex DWARF expressions. 2017-04-18 01:21:53 +00:00
InterferenceCache.cpp
InterferenceCache.h
InterleavedAccessPass.cpp InterleaveAccessPass: Avoid constructing invalid shuffle masks 2017-01-31 18:37:53 +00:00
IntrinsicLowering.cpp Module::getOrInsertFunction is using C-style vararg instead of variadic templates. 2017-04-11 15:01:18 +00:00
LatencyPriorityQueue.cpp
LazyMachineBlockFrequencyInfo.cpp [LazyMachineBFI] Reimplement with getAnalysisIfAvailable 2017-02-23 17:30:01 +00:00
LexicalScopes.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-17 21:43:25 +00:00
LiveDebugValues.cpp LiveDebugValues: Assume calls never clobber SP. 2017-03-03 01:08:25 +00:00
LiveDebugVariables.cpp Cleanup dump() functions. 2017-01-28 02:02:38 +00:00
LiveDebugVariables.h
LiveInterval.cpp RegisterCoalescer: Simplify subrange splitting code; NFC 2017-03-03 19:05:34 +00:00
LiveIntervalAnalysis.cpp Fix subreg value numbers in handleMoveUp 2017-03-11 00:14:52 +00:00
LiveIntervalUnion.cpp LIU:::Query: Query LiveRange instead of LiveInterval; NFC 2017-03-01 21:48:12 +00:00
LivePhysRegs.cpp Disable Callee Saved Registers 2017-03-14 09:09:26 +00:00
LiveRangeCalc.cpp RegisterCoalescer: Simplify subrange splitting code; NFC 2017-03-03 19:05:34 +00:00
LiveRangeCalc.h
LiveRangeEdit.cpp [LiveRangeEdit] Don't mess up with LiveInterval when a new vreg is created. 2017-02-02 20:44:36 +00:00
LiveRangeUtils.h
LiveRegMatrix.cpp LiveRegMatrix: Fix some subreg interference checks 2017-03-02 00:35:08 +00:00
LiveRegUnits.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-17 21:43:25 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp Cleanup dump() functions. 2017-01-28 02:02:38 +00:00
LLVMBuild.txt LLVMCodeGen: Add ProfileData into deps corresponding to r300277. 2017-04-14 00:36:06 +00:00
LLVMTargetMachine.cpp [GlobalISel] Add a way for targets to enable GISel. 2017-03-01 23:33:08 +00:00
LocalStackSlotAllocation.cpp
LowerEmuTLS.cpp
LowLevelType.cpp [GlobalISel] Support vector-of-pointers in LLT 2017-04-19 07:23:57 +00:00
MachineBasicBlock.cpp Refactor code to create getFallThrough method in MachineBasicBlock. 2017-03-31 15:55:37 +00:00
MachineBlockFrequencyInfo.cpp include function name in dot filename 2017-02-15 19:21:04 +00:00
MachineBlockPlacement.cpp CodeGen: BlockPlacement: Add comment about DenseMap Safety. 2017-04-12 18:30:32 +00:00
MachineBranchProbabilityInfo.cpp
MachineCombiner.cpp Fix up grammar in a comment. 2017-03-15 21:50:46 +00:00
MachineCopyPropagation.cpp MachineCopyPropagation: Respect implicit operands of COPY 2017-02-04 02:27:20 +00:00
MachineCSE.cpp
MachineDominanceFrontier.cpp
MachineDominators.cpp Do not verify MachimeDominatorTree if it is not calculated 2017-03-02 12:00:10 +00:00
MachineFrameInfo.cpp MachineFrameInfo: Move implementation to an own file; NFC 2017-04-26 23:36:58 +00:00
MachineFunction.cpp MachineFrameInfo: Move implementation to an own file; NFC 2017-04-26 23:36:58 +00:00
MachineFunctionPass.cpp Reverted: Track validity of pass results 2017-01-15 10:23:18 +00:00
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Cleanup: Use DIExpression::prepend in buildDbgValueForSpill(). (NFC) 2017-04-28 18:30:36 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp Remove tailing whitespaces. 2017-04-26 05:27:20 +00:00
MachineLoopInfo.cpp New OptimizationRemarkEmitter pass for MIR 2017-01-25 23:20:33 +00:00
MachineModuleInfo.cpp Implement FreeMachineFunction::getPassName(). 2017-03-07 20:59:08 +00:00
MachineModuleInfoImpls.cpp [WebAssembly] Add support for using a wasm global for the stack pointer. 2017-02-24 23:46:05 +00:00
MachineOptimizationRemarkEmitter.cpp [CodeGen] Teach opt remarks how to print MI instructions. 2017-02-23 21:05:33 +00:00
MachineOutliner.cpp Module::getOrInsertFunction is using C-style vararg instead of variadic templates. 2017-04-11 15:01:18 +00:00
MachinePassRegistry.cpp
MachinePipeliner.cpp Spelling mistakes in comments. NFCI. 2017-03-31 10:59:37 +00:00
MachinePostDominators.cpp
MachineRegionInfo.cpp Add MachineRegionInfoPassID to Passes.h. 2017-04-11 11:40:55 +00:00
MachineRegisterInfo.cpp [MIR] Support Customed Register Mask and CSRs 2017-03-19 08:14:18 +00:00
MachineScheduler.cpp MachineScheduler: Skip acyclic latency heuristic for in-order cores 2017-04-12 18:09:05 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-21 22:07:52 +00:00
MachineVerifier.cpp Do not run frame verification if target does not use frame instructions 2017-04-20 01:34:04 +00:00
MIRPrinter.cpp MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFC 2017-05-01 22:32:25 +00:00
MIRPrinter.h
MIRPrintingPass.cpp
OptimizePHIs.cpp
ParallelCG.cpp
PatchableFunction.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00
PeepholeOptimizer.cpp PeepholeOptimizer: Do not replace SubregToReg(bitcast like) 2017-01-09 21:38:17 +00:00
PHIElimination.cpp
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRAHazardRecognizer.cpp
PostRASchedulerList.cpp Cleanup dump() functions. 2017-01-28 02:02:38 +00:00
PreISelIntrinsicLowering.cpp
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp PEI: Skip dead objects when looking at CSRs 2017-05-02 18:56:28 +00:00
PseudoSourceValue.cpp Fix crashing on TargetCustom PseudoSourceValues 2017-03-28 20:33:12 +00:00
README.txt
RegAllocBase.cpp
RegAllocBase.h
RegAllocBasic.cpp LIU::Query: Remove always false member+getter; NFC 2017-03-01 21:02:52 +00:00
RegAllocFast.cpp Move size and alignment information of regclass to TargetRegisterInfo 2017-04-24 18:55:33 +00:00
RegAllocGreedy.cpp RegAllocGreedy: Follow-up to r296722 2017-03-03 23:27:20 +00:00
RegAllocPBQP.cpp Disable Callee Saved Registers 2017-03-14 09:09:26 +00:00
RegisterClassInfo.cpp Disable Callee Saved Registers 2017-03-14 09:09:26 +00:00
RegisterCoalescer.cpp RegisterCoalescer: Simplify subrange splitting code; NFC 2017-03-03 19:05:34 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Revert "Correct register pressure calculation in presence of subregs" 2017-02-24 21:56:16 +00:00
RegisterScavenging.cpp Move size and alignment information of regclass to TargetRegisterInfo 2017-04-24 18:55:33 +00:00
RegisterUsageInfo.cpp
RegUsageInfoCollector.cpp [IPRA] Change algorithm for RegUsageInfoCollector. 2017-03-13 21:42:53 +00:00
RegUsageInfoPropagate.cpp
RenameIndependentSubregs.cpp
ResetMachineFunctionPass.cpp GlobalISel: Abort in ResetMachineFunctionPass if fallback isn't enabled 2017-01-13 23:46:11 +00:00
SafeStack.cpp PR32382: Fix emitting complex DWARF expressions. 2017-04-18 01:21:53 +00:00
SafeStackColoring.cpp Cleanup dump() functions. 2017-01-28 02:02:38 +00:00
SafeStackColoring.h
SafeStackLayout.cpp
SafeStackLayout.h
ScheduleDAG.cpp MachineScheduler/ScheduleDAG: Add support for GetSubGraph 2017-03-28 05:12:31 +00:00
ScheduleDAGInstrs.cpp Refactor alias check from MISched into common helper. NFC. 2017-03-09 23:33:36 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-22 22:32:51 +00:00
ShadowStackGCLowering.cpp
ShrinkWrap.cpp
SjLjEHPrepare.cpp Module::getOrInsertFunction is using C-style vararg instead of variadic templates. 2017-04-11 15:01:18 +00:00
SlotIndexes.cpp VirtRegMap: Correctly deal with bundles when deleting identity copies. 2017-03-17 00:41:33 +00:00
Spiller.h
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp SplitKit: Fix subreg copy related problems 2017-03-21 21:58:08 +00:00
SplitKit.h SplitKit: Correctly implement partial subregister copies 2017-03-17 00:41:39 +00:00
StackColoring.cpp [StackColoring] Remove unused header file for post-order traversal. Update comment that indicated we were using it when we really use a depth-first search. NFC 2017-03-15 22:40:26 +00:00
StackMapLivenessAnalysis.cpp
StackMaps.cpp [StackMaps] Increase the size of the "location size" field 2017-04-28 04:48:42 +00:00
StackProtector.cpp Module::getOrInsertFunction is using C-style vararg instead of variadic templates. 2017-04-11 15:01:18 +00:00
StackSlotColoring.cpp In the below scenario, we must be able to skip the a DBG_VALUE instruction and 2017-01-09 17:45:02 +00:00
TailDuplication.cpp
TailDuplicator.cpp [TailDuplicator] Maintain DebugLoc for branch instructions 2017-02-27 19:30:01 +00:00
TargetFrameLoweringImpl.cpp Disable Callee Saved Registers 2017-03-14 09:09:26 +00:00
TargetInstrInfo.cpp Move size and alignment information of regclass to TargetRegisterInfo 2017-04-24 18:55:33 +00:00
TargetLoweringBase.cpp Do not legalize large add with addc/adde, introduce addcarry and do it with uaddo/addcarry 2017-04-30 19:24:09 +00:00
TargetLoweringObjectFileImpl.cpp [ProfileData] Unify getInstrProf*SectionName helpers 2017-04-15 00:09:57 +00:00
TargetOptionsImpl.cpp Remove LessPreciseFPMADOption from TargetOptions along with all of the 2017-03-17 00:38:03 +00:00
TargetPassConfig.cpp Allow targets to opt-in to codegen in SCC order 2017-04-04 23:44:46 +00:00
TargetRegisterInfo.cpp Move value type list from TargetRegisterClass to TargetRegisterInfo 2017-04-24 19:51:12 +00:00
TargetSchedule.cpp This patch closes PR#32216: Better testing of schedule model instruction latencies/throughputs. 2017-04-14 07:44:23 +00:00
TargetSubtargetInfo.cpp This patch closes PR#32216: Better testing of schedule model instruction latencies/throughputs. 2017-04-14 07:44:23 +00:00
TwoAddressInstructionPass.cpp [TwoAddressInstruction] Fix typo in comment. NFC 2017-02-04 01:58:10 +00:00
UnreachableBlockElim.cpp Properly handle PHIs with subregisters in UnreachableBlockElim 2017-04-28 21:56:33 +00:00
VirtRegMap.cpp Move size and alignment information of regclass to TargetRegisterInfo 2017-04-24 18:55:33 +00:00
WinEHPrepare.cpp Allow DataLayout to specify addrspace for allocas. 2017-04-10 22:27:50 +00:00
XRayInstrumentation.cpp [LLVM][XRAY][MIPS] Support xray on mips/mipsel/mips64/mips64el 2017-02-15 10:48:11 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.